Tessent products

Deliver the highest quality deterministic scan test with the lowest manufacturing test cost, using patented on-chip compression to reduce test data volume and cut test time.

Automate the generation and insertion of IEEE 1838-compliant hardware and define the IEEE test access architecture for 3D stacked integrated circuits.

Reduce DFT development time and manufacturing test cost by decoupling core-level and chip-level DFT requirements with Tessent Streaming Scan Network (SSN).

Enable comprehensive automation and integration of test, repair, debug, and characterization of embedded memories with Tessent MemoryBIST.

Enable ISO 26262 compliance with the ideal logic built-in self-test solution for safety-critical devices such as ICs used in automotive and medical applications.

Combine automation and on-chip IP to enable IC test and diagnosis at any point during a vehicle’s functional operation – a fundamental requirement of the ISO 26262 standard.

Reduce DFT implementation effort with an optimal automation of the Tessent Platform flow for hierarchical DFT.

Improve test compression levels up to 4X, enable hierarchical DFT, logic BIST readiness and scan insertion with Tessent ScanPro.

Streamline a broad array of critical DFT tasks with this new software developed for IC design teams.

Simplify the process of generating high-coverage compact test sets. The ability of Tessent FastScan to be applied to most any type of design makes it the most versatile ATPG solution available.

Provide automation and integration for IEEE 1687 IJTAG compliant test and instrumentation IP from various sources into an IC design.

Automate the addition of IEEE 1149.1 standard boundary scan support to ICs of any size or complexity, reducing development effort and improving time-to-market.

Simulate transistor-level defects for analog, mixed-signal and non-scan digital circuits, automating coverage assessment to help meet quality standards such as ISO 26262.

Apply layout-aware and cell-aware diagnosis technologies to accurately classify and identify the location of defects causing failures during manufacturing tests.

Accelerate test bring-up, debug and silicon characterization of devices containing Tessent ATPG, EDT, BIST and/or IJTAG test structures within an automated interactive environment.

Eliminate noise from diagnosis data to determine the underlying root causes, identify systematic yield limiters and select the best devices for failure analysis.

Design with a solution made to meet the official RISC-V trace specification: Tessent Enhanced Trace Encoder.

Accelerate debug, validation and optimization of complex multicore SoCs. Leverage embedded, non-intrusive instrumentation to allow for observation of what’s happening in the design when software is running on the system.

Allow application software running on an SoC to monitor operations effectively. Allow products to be successively refined and optimized based on data gathered in real-life usage – not just in the lab.

Ensure the highest manufacturing test quality with Tessent solutions. Maximize the number of detected physical defects in your zero-defect test solution.

Reduce risk and meet required safety standards with comprehensive in-system test and fault grading solutions, ensuring that your product is fully compliant for the safety-critical applications it is designed for.

Implement a comprehensive security solution for your IC product, addressing authentication, communication, protection and device lifecycle management across test, functional operation and system-level security.

Diagnose and analyze failure and yield data on individual customer returns or volume production data. Get valuable design and process feedback to improve the reliability of future processes and designs.