Next-generation devices increasingly feature complex architectures that connect dies vertically (3D IC) or side-by-side (2.5D) so that they behave as a single device. Tessent Multi-die delivers comprehensive automation for the highly complex DFT tasks associated with these 2.5D and 3D IC designs.
Siemens' Tessent multi-die software helps customers dramatically speed and simplify critical design-for-test (DFT) tasks for next-generation integrated circuits (ICs) based on 2.5D and 3D architectures.
The demand for smaller, higher-performing and more power-efficient integrated circuits (ICs) continues. Next-generation devices often feature complex 2.5D and 3D architectures that connect dies side-by-side (2.5D) or vertically (3D IC), also known as 3D stacking. Densely packed dies in 2.5D and 3D devices present significant challenges for IC test with legacy approaches built using conventional two-dimensional processes.
Siemens' Tessent™ Multi-die software addresses these challenges with a comprehensive DFT automation solution for highly complex tasks associated with 2.5D and 3D IC designs. Tessent Multi-die works seamlessly with Tessent TestKompress™ Streaming Scan Network and IJTAG software. Teams can optimize DFT test resources for each block without concern for impacts to the rest of the design–streamlining DFT planning and implementation for the 2.5D and 3D IC era.
Tessent Multi-die software helps customers speed and simplify critical design-for-test (DFT) tasks for next-generation ICs based on 2.5D and 3D architectures. Faster, simpler DFT enables IC design teams to generate compliant hardware rapidly.
DFT technology that keeps pace with multi-dimensional designs enables customers to slash test implementation efforts and optimize manufacturing test costs.
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