An integrated IC packaging solution that covers everything from planning and prototyping to signoff for various integration technologies such as FCBGA, FOWLP, 2.5/3D IC, and others. Our IC packaging solutions help you overcome the limitations of monolithic scaling.
The semiconductor industry has made great strides in ASIC technology over the last 40 years, leading to better performance. But as Moore's law nears its limits, scaling devices is becoming harder. Shrinking devices now takes longer, costs more, and presents challenges in technology, design, analysis, and manufacturing. Thus, enters 3D IC.
Tackle 3D IC integration and packaging with system co-optimization to balance requirements and resources and gain visibility into downstream impact to PPA and cost.
Enable digital transformation for 3D chip design with co-design, co-simulation and automated system analysis and checking. Replace manual interfaces and data exchanges with automated methods and defined workflows.
Comprehensive 3D IC packaging coverage for performance validation and design verification from predictive to final sign off. Automated reviews identify overt issues earlier in the chip design process and eliminate iterations.
Support team-based design for concurrent development and enable IP reuse and managed blocks. Leverage one chiplet layout tool for organic and silicon substrates for better advanced packaging design.
The Siemens 3D IC heterogeneous semiconductor packaging workflows catapult design teams into the future of IC design today.
37% Growth Chiplet design starts (7nm and below) are growing at 37% CAGR from 2023 to 2030 (Source: IBS)
More than 600 million chiplet based packages will be manufactured by 2025 (source: Techsearch International)
The worlds Top 3 OSATs use Siemens software for their advanced semiconductor packaging technologies. (ASE, Amkor and SPIL)
Company:ETRI and Amkor
Industry:Electronics, Semiconductor devices
Location: USA, South Korea
Siemens Software:Calibre, Xpedition IC Packaging
3D IC is a new design paradigm driven by the diminishing returns of IC technology scaling, AKA Moore’s Law. 3D IC leverages new advanced packaging technologies that enable the integration of one or more chiplets into a single package. Chiplets are integrated circuits (IC) optimized for integration into a single package.
3D IC designs require the seamless integration of multi-domain ECAD/MCAD tools within a highly integrated, design platform, referred to as 3D IC workflows. Leveraging Siemens’ broad portfolio of leading EDA and MCAD tools, a comprehensive set of workflows are offered spanning the spectrum from system level decomposition to manufacturing handoff to empower its customers to design these complex, chiplet-based designs.
The 3D IC workflows also require tight integration with a comprehensive set of design kits to enable the design, integration, and assembly of chiplet-based 3D IC designs. To enable a chiplet ecosystem, Siemens has taken leadership in driving the new CDX/OCP 3D IC Design Kits (3DK) initiatives in collaboration with other EDA vendors. Siemens is sponsoring and actively driving the adoption of these new industry standards by the JEDEC industry standards body and is committed to formally adopt these new standards in its tools and workflows.
3D IC technology enables a system-based approach to decompose an electronic system or subsystem into a chiplet based system in package (SiP) design which offers increased performance, lower cost, reduced form factor and more flexible, cost-effective product variants.
The Siemens 3D IC workflows support architectural planning/analysis, physical design planning/verification, electrical and reliability analysis, and test/diagnostic support through manufacturing handoff.
The workflows integrate and back-annotate the electrical/reliability analysis results into the design planning/implementation tools enabling designers to run early predictive, in-design, and sign-off analysis. This new predictive analysis capability provides designers an early look at performance and reliability to facilitate architectural exploration before executing extensive physical design resources. In-design analyses enables design teams to interactively run checks during the design process and make design changes as needed rather than waiting for sign-off checks to be run on completed designs. The signoff checks are run on the final design to ensure functionality, performance, and reliability/manufacturability of the design exemplars before release to manufacturing.
The Siemens 3D IC solutions include five workflows that support architectural planning and analysis, physical design and verification, electrical analysis, reliability analysis and 3D IC Test planning and analysis support. Additionally, an integrated mechanical design and analysis workflow is available to support mechanical package design and system level, thermal/mechanical signoff level analysis. Although Siemens includes all the required tools for the respective workflows, the modular architecture supports the integration of additional best is class and/or incumbent customer tools and workflows.
Siemens offers best in class package planning and 3D stack validation tools in the 3D IC design workflows. The integrated electrical and reliability workflow support early predictive, in-design and signoff analysis of multi-layer 2.5/3D designs. The test workflows facilitate collaboration between the package/chiplet design teams with the DFT/test teams leveraging the best-in-class Siemens multi-die DFT tool suite.
3D IC technology offers the system designer nearly unlimited flexibility to partition their design into chiplets each optimized in an IC technology node best suited for each function. The architectural planning and design workflows facilitate collaboration between the system/RTL design teams with the package/chiplet design teams leveraging predictive analysis to efficiently home in on an optimal architecture prior to deploying expensive and time-consuming design implantation on potentially non-optimal or pathological design.
In-design analysis enables the physical design and electrical/reliability analysis teams to validate the design during the implementation phases, catching errors prior to signoff checks run on completion of the physical design thus avoiding rework and related schedule delays.
Careful, up front and validated DFT/test workflow enable timely test bring up during the new product introduction (NPI) phase of the program enabling earlier entry to market of semiconductor products.