3D IC design solutions
Explore and deliver product differentiation faster using 3D heterogeneous integration of node and performance-optimized chiplets with Siemens EDA's marketing-leading 3D IC solution
Explore and deliver product differentiation faster
Expand revenue streams by transforming existing design and IP architectures into chiplets or build scalable 3D IC platforms for faster TTM. Engineer a smarter future with a proven and complete flow from 3D IC architecture partitioning to planning, layout, design-for-test, verification, analysis, manufacturing signoff, and post-silicon lifecycle monitoring with Siemens EDA’s market-leading 3D IC solution.
Key benefits for Siemens 3D IC design flow tools
Unlike design-level, system co-optimization balances requirements and resources across multi-domains, requiring visibility into downstream effects on PPA and cost.
Digital transformation
Enable digital transformation through co-design, co-simulation, and automated checking. Replace manual interfaces and data exchanges with more automated methods and defined workflows.
Faster verification and validation
Most comprehensive coverage for performance validation and design verification - from predictive through in-process to final signoff. Automated reviews identify overt issues earlier in the process and eliminate iterations.
Better resource utilization
Support team-based design for concurrent development and enable IP reuse and managed blocks. Leverage one layout tool for organic and silicon substrates for better package design organization.
3D IC design flow tools and IC packaging solutions
3D IC Design Flow is a comprehensive set of tools and workflows targeted to develop advanced 2.5/3D IC heterogeneous System-In-Package (SIP) designs.
- Enables the RTL architect to design and collaborate with the packaging team to explore viable SiP level scenarios.
- Develop and assess the pros and cons of multiple architectural to technology scenarios pre-design.
- Architectural partitioning of functions and selection of appropriate die-2-die interfaces, protocols, and memory interfaces
- Logical synthesis maps initial generic IP to specific IP
- Creation and validation of system-level logical netlist
- Predictive analysis
- Enables efficient STCO-driven physical planning, optimization, and detailed implementation with comprehensive physical verification.
- Leverage a single, integrated design, verification, and signoff workflow for optimal productivity.
- Single cockpit for integrated planning and co-design optimization across chiplets, ASICs, interposers, and package substrates
- Uses a single workflow to support the design of interposers, RDL build-up, and organic substrate technologies
- Robust ECO data exchange flow with the place and route tools
- Comprehensive functional and physical verification
- Provides complete electrical modeling and analysis from extraction to sign and power integrity through static timing analysis.
- Comprehensive and proven signal, power, 3DEM, and static timing analysis and verification.
- Integrated 3D parasitic extraction across silicon and organic substrates
- System-level signal and power integrity analysis
- Comprehensive infrared (IR) drop and electromagnetic (EM) analysis
- System-level static timing analysis and simulation
- Complete 2.5 and 3D integration test coverage for all levels of chiplet, ASIC, interposer, and package substrates.
- Use a single integrated and comprehensive test planning and implementation solution for all levels of 2.5/3D package assembly.
- ASIC DFT planning and validation with SSN/JTAG bus planning/routing and probe pad planning
- BSCAN/TAP and SSN across 2.5 and 3D
- Die-2-die and die pattern test retargeting
- Thermal and thermally induced mechanical stress analysis with co-simulation and optimization.
- Use a single integrated and comprehensive test planning and implementation solution for all levels of 2.5/3D package assembly.
- Chiplet, ASIC, interposer, package level thermal and stress analysis
- DFM substrate fabrication verification
- Thermo-mechanical co-simulation and optimization
The future of semiconductor design
Learn more from industry experts on topics related to three-dimensional integrated circuits and how they deliver higher performance.
