ADVANCED 3D IC DESIGN FLOW
3D IC design solutions
Explore and deliver product differentiation faster using 3D heterogeneous integration of node and performance-optimized chiplets with Siemens EDA's market-leading 3D IC technology solution.
Explore and deliver product differentiation faster
Engineer a smarter future with a proven, complete 3D IC design flow from 3D architecture partitioning to planning, layout, design-for-test, thermal management, multi-die verification, interconnect IP, manufacturing signoff, and post-silicon lifecycle monitoring. Transform existing design and IP architectures into chiplets or build scalable 3D IC technology for faster TTM.
Key benefits for Siemens 3D IC design flow tools
Tackle 3D IC integration and packaging with system co-optimization to balance requirements and resources and gain visibility into downstream impact to PPA and cost.
3D IC digital transformation
Enable digital transformation for 3D chip design with co-design, co-simulation and automated system analysis and checking. Replace manual interfaces and data exchanges with automated methods and defined workflows.
3D IC verification and validation
Comprehensive 3D IC packaging coverage for performance validation and design verification from predictive to final sign off. Automated reviews identify overt issues earlier in the chip design process and eliminate iterations.
Better 3D IC design resource utilization
Support team-based design for concurrent development and enable IP reuse and managed blocks. Leverage one chiplet layout tool for organic and silicon substrates for better advanced packaging design.
3D IC design flow tools and IC packaging solutions
3D IC Design Flow is a comprehensive set of tools and workflows targeted to develop advanced 2.5/3D IC heterogeneous System-In-Package (SIP) designs.
3D IC Architect workflow
- Enables the RTL architect to design and collaborate with the packaging team to explore viable SiP level scenarios.
- Develop and assess the pros and cons of multiple architectural to technology scenarios pre-design.
- Architectural partitioning of functions and selection of appropriate die-2-die interfaces, protocols, and memory interfaces
- Logical synthesis maps initial generic IP to specific IP
- Creation and validation of system-level logical netlist
- Predictive analysis
3D IC Designer workflow
- Enables efficient STCO-driven physical planning, optimization, and detailed implementation with comprehensive physical verification.
- Leverage a single, integrated design, verification, and signoff workflow for optimal productivity.
- Single cockpit for integrated planning and co-design optimization across chiplets, ASICs, interposers, and package substrates
- Uses a single workflow to support the design of interposers, RDL build-up, and organic substrate technologies
- Robust ECO data exchange flow with the place and route tools
- Comprehensive functional and physical verification
3D IC Analysis workflow
- Provides complete electrical modeling and analysis from extraction to sign and power integrity through static timing analysis.
- Comprehensive and proven signal, power, 3DEM, and static timing analysis and verification.
- Integrated 3D parasitic extraction across silicon and organic substrates
- System-level signal and power integrity analysis
- Comprehensive infrared (IR) drop and electromagnetic (EM) analysis
- System-level static timing analysis and simulation
3D IC Test workflow
- Complete 2.5 and 3D integration test coverage for all levels of chiplet, ASIC, interposer, and package substrates.
- Use a single integrated and comprehensive test planning and implementation solution for all levels of 2.5/3D package assembly.
- ASIC DFT planning and validation with SSN/JTAG bus planning/routing and probe pad planning
- BSCAN/TAP and SSN across 2.5 and 3D
- Die-2-die and die pattern test retargeting
3D IC Reliability workflow
- Thermal and thermally induced mechanical stress analysis with co-simulation and optimization.
- Use a single integrated and comprehensive test planning and implementation solution for all levels of 2.5/3D package assembly.
- Multi-die, chiplet, ASIC, interposer, package level thermal and stress analysis
- DFM substrate fabrication verification
- Thermo-mechanical co-simulation and optimization
The future of semiconductor design
Listen to industry experts discuss 3D IC concepts and the latest trends: chiplet designs, IC packaging, multi-die verification, golden netlists, electrical signoff, system analysis and more!
3D IC Resource Library
View the 3D IC resource library for white papers, webinars, articles and more on proposed chiplet standardization, system-level netlists and verification, and advanced packaging.
