Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.
Xpedition IC Packaging VX.2.11 delivers capabilities targeting heterogeneous integration and the prototyping, planning, design, and verification of next-generation 2.5/3D package assemblies.
Xpedition IC Packaging VX.2.10 delivers capabilities targeted at prototyping, planning, and designing next-generation 2.5/3D heterogeneous packages. Learn about all of the new features and enhancements of the VX.2.10 release.
System Technology Co-Optimization (STCO) driven prototyping and planning deliver heterogeneous integration that meets PPA goals.
A complete solution for the physical implementation of High-Density Advanced Packages (HDAP), such as FOWLP, 2.5/3D, and SiP technologies.
Comprehensive PEX, EM modeling, SI/PI, and thermal/stress analysis.
The industry’s most trusted technology, Calibre, provides the foundation for a comprehensive package assembly-level verification and signoff solution.
Explore and deliver product differentiation faster using 3D heterogeneous integration of node and performance-optimized chiplets with Siemens EDA's marketing-leading 3D IC solution.
Graphical virtual prototyping and planning environment tuned for the exploration and integration of heterogeneous ASIC/chiplets and interposers using System Technology Co-Optimization (STCO) with predictive multi-physics analysis.
Complete physical design and verification solution. Supports heterogeneous integration using the latest silicon and wafer-based technologies such as RDL fan-out wafer-level packaging (FOWLP) and 2.5D/3DIC.
Complete design verification and signoff of heterogeneously integrated assemblies using foundry/OSAT supplied assembly design kits (ADK). Direct integration with Xpedition Package Designer streamlines tapeout readiness.