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Complete solution for IC package design

IC packaging design & verification

Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.

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What’s new in Xpedition IC Packaging VX.2.11

Xpedition IC Packaging VX.2.11 delivers capabilities targeting heterogeneous integration and the prototyping, planning, design, and verification of next-generation 2.5/3D package assemblies.

What’s new in Xpedition IC Packaging VX.2.10

Xpedition IC Packaging VX.2.10 delivers capabilities targeted at prototyping, planning, and designing next-generation 2.5/3D heterogeneous packages. Learn about all of the new features and enhancements of the VX.2.10 release.

IC packaging solutions

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Heterogeneous co-optimization

2.5/3D substrate integration

System Technology Co-Optimization (STCO) driven prototyping and planning deliver heterogeneous integration that meets PPA goals.

Multi substrate implementation

Package design

A complete solution for the physical implementation of High-Density Advanced Packages (HDAP), such as FOWLP, 2.5/3D, and SiP technologies.

Multi-physics analysis

Package simulation

Comprehensive PEX, EM modeling, SI/PI, and thermal/stress analysis.

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Physical verification/signoff

3D DRC/LVS verification

The industry’s most trusted technology, Calibre, provides the foundation for a comprehensive package assembly-level verification and signoff solution.

Advanced 3D IC design flow

3D IC design solutions

Explore and deliver product differentiation faster using 3D heterogeneous integration of node and performance-optimized chiplets with Siemens EDA's marketing-leading 3D IC solution.

Featured products

Xpedition Substrate Integrator

Graphical virtual prototyping and planning environment tuned for the exploration and integration of heterogeneous ASIC/chiplets and interposers using System Technology Co-Optimization (STCO) with predictive multi-physics analysis.

Xpedition Package Designer

Complete physical design and verification solution. Supports heterogeneous integration using the latest silicon and wafer-based technologies such as RDL fan-out wafer-level packaging (FOWLP) and 2.5D/3DIC.

Calibre 3DSTACK

Complete design verification and signoff of heterogeneously integrated assemblies using foundry/OSAT supplied assembly design kits (ADK). Direct integration with Xpedition Package Designer streamlines tapeout readiness.