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IC Packaging Design & Verification
<p>Complete Solution for IC Package Design</p>
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Drive for Emerging Technologies

Cost, risk, and monolithic scaling limitations drive the growth of multi-die heterogeneous and homogeneous advanced IC packaging solutions. By bringing the traditional IC and IC package design worlds together, a comprehensive HDAP flow meets the unique challenges of HDAP design and verification.

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Substrate Co-Optimization

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Multi-Substrate Integration

To minimize layer count and keep package and PCB costs low without impacting the cost of the device, ICs, substrates, and PCBs must be optimized within the context of each other.

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Package Design - Multi Substrate Implementation, software design image with lines

Multi Substrate Implementation

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Package Design

A complete solution for physical implementation of High Density Advanced Packages (HDAP), such as FOWLP, 2.5/3D, and SiP technologies.

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Physical Verification/Signoff

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Comprehensive Verification

The Xpedition HDAP flow offers complete design verification of stacked die assemblies, such as stacked memories, stacked sensor arrays, interposer-based structures, and fan-out wafer-level packaging.

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Explore IC Packaging & Verification Challenges

Today's high-performance products demand advanced IC packaging. These products require heterogeneous silicon (chiplets) to be integrated into multi-chip, wafer-based HDAP packages, such as FOWLP, 2.5/3DIC, SiP, and CoWoS. These packages must be optimized for the target system’s PCB(s).

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IC Packaging Challenges

Design & Foundry Flows to OSAT Alliance
Image of a man holding IC chip

IC Packaging Challenges

Design & Foundry Flows to OSAT Alliance
Image of a man holding IC chip

IC Packaging Challenges

Design & Foundry Flows to OSAT Alliance

Featured Products

Xpedition Substrate Integrator / diagram of multi-chip package

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Xpedition Substrate Integrator

Heterogeneous and homogeneous 2.5/3D system connectivity IC package planning and prototyping for evaluating different IC, interposer, package, and PCB integration scenarios.

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Xpedition Package Designer

Provides a complete physical design solution, including flip chip and/or wirebond attach, stacked die, heterogeneous integration, and multi-device System-In-Package (SiP) or modules.

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Calibre 3DSTACK

Complete design verification of stacked die assemblies, such as stacked memories, stacked sensor arrays, interposer-based structures, and fan-out wafer-level packaging.

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