Siemens Digital Industries Software has collaborated with leading Outsourced Assembly and Test (OSAT) company Siliconware Precision Industries Co., Ltd. (SPIL) to develop and implement a new integrated circuit (IC) package assembly planning and 3D layout vs. schematic (LVS) assembly verification workflow for SPIL’s fan-out family of advanced IC packaging technologies.
To get ahead in advanced IC packaging, companies need to consider six key pillars for success.
Multi chiplet/ASIC packages with heterogenous integration drive the need for early assembly floorplanning if power, performance, area and cost targets are to be achieved.
With the complexity of today’s emerging semiconductor packages, design teams need to utilize multiple skilled design resources concurrently and asynchronously in order to meet schedules and manage development costs.
Getting to market faster requires that you have seamless interoperability between the key processes of routing, tuning and metal area fill that deliver results that require minimal signoff cleanup.
By using automation and intelligent design-IP replication, designs targeting HPC and AI markets have an increased likelihood of meeting design schedules and quality targets.
With the complexity of today’s IC packages design teams can benefit from true 3D design visualization and editing.
As multi chiplet/ASIC designs scale into multi million-pin assemblies it crucial that the design tools can handle this capacity while still delivering productivity and usability.
Today, IC package design teams must deliver more complex designs with heterogeneous integration that use multiple chiplets/ASICs in order address the inflection point of higher semiconductor cost, lower yield, & reticle size limitations.
Multi chiplet/ASIC packages with heterogeneous integration demand early assembly floorplanning if power, performance, area and cost targets are to be achieved. Architects and designers can define optimize complete package assemblies for power, performance, area and cost and deliver a well-qualified prototype for implementation.
Complex multi chiplet/ASIC designs with memory are often integrated using interposers or embedded or elevated bridges making the design very challenging for a single user, not just because of the sheer size but also the need for multiple skills. Multi-user concurrent design enables teams of designers to collaborate together, leverage skills to get the design completed efficiently, on schedule and meet quality and performance goals.
Whatever advanced packaging technology you are designing it will require complex metal filled planes and shapes. Your substrate fabricator will have given you strict guidelines on outgassing void insertions, metal density balancing, power/ground ball/bump thermal ties. Its imperative that you can design with signoff quality results in real-time and not have to endure post-processing workarounds. To meet you project goals you need seamless interoperability between signal routing, route tuning and all metal area fill creation/editing operations.
The digital transformation of society and economy is creating an increasing demand to transfer, process and store vast amounts of data generated in the context of technologies such as high-performance computing (HPC), artificial intelligence (AI) and the Internet of Things (IoT). To enable the processing of such data architects are turning to high bandwidth memory (HBM) which offers lower power and substantially smaller form factors than DDR*. HBM’s memory bus is very wide, consists of multiple channel and can be challenging and time consuming to design. By using automation and intelligent design-IP channel replication designers can easily meet design schedules, performance and quality targets.
Multi chiplet/ASIC packages with heterogeneous integration typically utilize substrates for high-speed integration, package BGAs for the connection to the systems PCB and include items such as mechanical substrate stiffeners and thermal interface materials and heat spreaders. The entire package assembly can look like a Manhattan skyline with a lot happening in the Z-axis. With all this vertical complexity design teams can no longer effectively design using traditional 2D tools with 2D views. Having the ability to visualize and edit in photo-realistic 3D reduces errors, shrinks design cycles and reduce designer frustration.
When designing a high performance heterogeneously integrated semiconductor package its likely to include multiple logic chiplets/ASICs and HBM memory stacks. It will contain at least one interposer and most likely be mounted onto a BGA package. This entire device assembly can easily exceed a million or more total pins, in fact we have customer examples of 10+ million total pins. With such a volume of design objects it is crucial that your design tools can handle the capacity while still delivering productivity and usability.