{"showBreadcrumbs":true,"breadcrumbs":[{"title":"Siemens EDA Software","path":"/en-US/"},{"title":"IC Packaging","path":"/en-US/ic-packaging"},{"title":"IC Packaging Solutions","path":"/en-US/ic-packaging/software"},{"title":"Package Simulation","path":""}],"tagline":"Overview","title":"Package Simulation","description":"Comprehensive analysis of die/package coupling, signal integrity/PDN performance, and thermal conditions. SI/PDN issues are found, investigated, and validated. 3D thermal modeling and analysis predicts airflow and heat transfer in and around electronic systems.","pricingCurrency":"US$","image":{"url":"//images.ctfassets.net/17si5cpawjzf/3KF9XnMkcn6YpkOCjWCA6M/e1abc4300367ceffeea1890fafe10130/package-simulation-promo-640x480.jpg?w=640","alt":"package-simulation","linkData":"{\"name\":\"package-simulation-promo-640x480\",\"id\":\"3KF9XnMkcn6YpkOCjWCA6M\",\"contentType\":\"image/jpeg\"}"},"secondaryButton":{"text":"Read White Paper","url":"https://resources.sw.siemens.com/en-US/white-paper-system-level-post-layout-electrical-analysis-for-high-density-advanced","resource":{"ids":[],"mode":"selected","query":{"q":"System-level, post-layout electrical","sorts":[{"field":"publishedDate","order":"desc"}],"filters":[{"field":"collection","values":["resource"],"operator":"OR"}],"postFilters":[{"field":"resourceType","values":["White Paper","techpub"],"operator":"OR"}],"verboseLocalization":true},"idsQuery":{"size":0,"filters":[{"field":"collection","values":["resource"],"operator":"OR"},{"field":"id","values":[],"operator":"OR"}],"verboseLocalization":true}},"env":"master"},"phoneIcon":true,"moreInformation":"Get in touch with our sales team 1-800-547-3000"}
Overview

Package Simulation

Comprehensive analysis of die/package coupling, signal integrity/PDN performance, and thermal conditions. SI/PDN issues are found, investigated, and validated. 3D thermal modeling and analysis predicts airflow and heat transfer in and around electronic systems.


Get in touch with our sales team 1-800-547-3000

package-simulation
Key Features

Voltage Drop and IC Switching Noise Analysis

Identify areas of excessive current density and the effects of switching noise as it propagates through planes and vias.

Comprehensive SERDES Support

Advanced tools for optimizing SERDES design projects, including FastEye diagram analysis, S-parameter simulation, and BER prediction.

SERDES

High Performance Parasitic Extraction

System circuitry, including parasitics, in analog designs must be simulated to ensure it meets intended performance specifications. In digital designs, static timing analysis (STA) must be run on the complete package assembly, including parasitics, to ensure it meets the overall system timing budget.

calibrex act

IC, Package & PCB Thermal Modeling

Heterogeneous IC-package co-design is important for several reasons. Designing a large high-power device, e.g. an AI or HPC processor, without considering how to get the heat out is likely to lead to problems later on, resulting in a sub-optimal packaging solution from cost, size, weight, and performance perspectives.

thermal modeling

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{"desc":"This site uses cookies in order to improve your user experience and to provide content tailored specifically to your interests. Detailed information on the use of cookies on this website is provided in our Privacy Policy. You can also manage your preferences there. By using this website, you consent to the use of cookies.","learnMoreText":"Learn More","learnMoreUrl":"https://new.siemens.com/global/en/general/cookie-notice.html","okText":"OK"}