Package Signoff
Design verification of multiple die and substrate assemblies by identifying geometries per layer per die placement in the assembly. DRC and LVS is performed on the interface geometries between die with support for dies from multiple processes.
Foundry/OSAT Driven Substrate Verification
When performance and time-to-market control potential profitability, using Calibre nmDRC for your physical verification enables success. Continually evolving to meet the demands of shrinking geometries and complex manufacturing methodologies, Calibre rule decks are proven long before you need them.
Signoff Verification of 2.5/3D Stacked Die Assemblies
Provides complete design verification of stacked die assemblies and delivers 3D assembly LVS for assemblies such as stacked memories, stacked sensor arrays, interposer-based structures, and package-level RDL routing (wafer-level packaging). Errors and issues are cross-probed directly into the design for immediate attention.
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