Foundry-specific process flows that are built, tested, and certified
Graphical virtual prototyping & planning environment tuned for the exploration and integration of heterogeneous ASIC/chiplets and interposers using System Technology Co-Optimization (STCO) with predictive multi-physics analysis.
Complete physical design and verification solution. Supports heterogeneous integration using the latest silicon and wafer-based technologies such as RDL fan-out waferlevel packaging (FOWLP) and 2.5D/3DIC.
Complete design verification and signoff of heterogeneous integrated assemblies using foundry/OSAT supplied assembly design kits (ADK) Direct integration with Xpedition Package Designer streamlines tapeout readiness.