Foundry-specific process flows that are built, tested, and certified
TSMC Certified Reference Flows
Taiwan Semiconductor Manufacturing Company (TSMC®) is the world’s largest dedicated semiconductor foundry. TSMC offers multiple advanced IC packaging technologies for which the Siemens EDA IC packaging design solution has been certified.
TSMC certified reference flows
Advanced IC packaging is critical to industries where high-performance is mandatory.
Integrated Fanout (InFO)
Supports single, multi-die or package-on-package. Complete prototyping, design and verification certified.
Chip on Wafer on Substrate (CoWoS)
Integrates logic and memory in 3D targeting, AI, HPC. Xpedition Substrate Integrator creates, optimizes & manages a 3D model.
Wafer on Wafer (WoW)
Xpedition Substrate Integrator creates, optimizes, and manages a 3D model that drives design.
System-on-Integrated Chips (SoIC)
Xpedition Substrate Integrator optimizes and manages a 3D model that drives design then verification with Calibre 3DSTACK.
TSMC certified reference flows
Advanced IC packaging is critical to industries where high-performance is mandatory.
Integrated Fanout (InFO)
Supports single, multi-die or package-on-package. Complete prototyping, design and verification certified.
Chip on Wafer on Substrate (CoWoS)
Integrates logic and memory in 3D targeting, AI, HPC. Xpedition Substrate Integrator creates, optimizes & manages a 3D model.
Wafer on Wafer (WoW)
Xpedition Substrate Integrator creates, optimizes, and manages a 3D model that drives design.
System-on-Integrated Chips (SoIC)
Xpedition Substrate Integrator optimizes and manages a 3D model that drives design then verification with Calibre 3DSTACK.
TSMC certified reference flows
Advanced IC packaging is critical to industries where high-performance is mandatory.
Integrated Fanout (InFO)
Supports single, multi-die or package-on-package. Complete prototyping, design and verification certified.
Chip on Wafer on Substrate (CoWoS)
Integrates logic and memory in 3D targeting, AI, HPC. Xpedition Substrate Integrator creates, optimizes & manages a 3D model.
Wafer on Wafer (WoW)
Xpedition Substrate Integrator creates, optimizes, and manages a 3D model that drives design.
System-on-Integrated Chips (SoIC)
Xpedition Substrate Integrator optimizes and manages a 3D model that drives design then verification with Calibre 3DSTACK.
Integrated Fanout (InFO)
Supports single, multi-die or package-on-package. Complete prototyping, design and verification certified.
Chip on Wafer on Substrate (CoWoS)
Integrates logic and memory in 3D targeting, AI, HPC. Xpedition Substrate Integrator creates, optimizes & manages a 3D model.
Wafer on Wafer (WoW)
Xpedition Substrate Integrator creates, optimizes, and manages a 3D model that drives design.
System-on-Integrated Chips (SoIC)
Xpedition Substrate Integrator optimizes and manages a 3D model that drives design then verification with Calibre 3DSTACK.
Integrated Fanout (InFO)
Supports single, multi-die or package-on-package. Complete prototyping, design and verification certified.
Chip on Wafer on Substrate (CoWoS)
Integrates logic and memory in 3D targeting, AI, HPC. Xpedition Substrate Integrator creates, optimizes & manages a 3D model.
Wafer on Wafer (WoW)
Xpedition Substrate Integrator creates, optimizes, and manages a 3D model that drives design.
System-on-Integrated Chips (SoIC)
Xpedition Substrate Integrator optimizes and manages a 3D model that drives design then verification with Calibre 3DSTACK.
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