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IC Packaging Design Flows

Today's high-performance products require advanced IC packaging that utilizes heterogeneous silicon (chiplets) to be integrated into multi-chip, wafer-based HDAP packages. Different vertical markets often have specific needs and corresponding design flows as shown below.

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Xpedition Substrate Integrator / diagram of multi-chip package
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Xpedition Substrate Integrator

Graphical virtual prototyping and planning environment tuned for the exploration and integration of heterogeneous ASIC/chiplets and interposers using System Technology Co-Optimization (STCO) with predictive multi-physics analysis.

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Xpedition Package Designer

Complete physical design and verification solution. Supports heterogeneous integration using the latest silicon and wafer-based technologies such as RDL fan-out wafer-level packaging (FOWLP) and 2.5D/3DIC.

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Calibre 3DSTACK

Complete design verification and signoff of heterogeneously integrated assemblies using foundry/OSAT supplied assembly design kits (ADK). Direct integration with Xpedition Package Designer streamlines tapeout readiness.