IC Packaging Design Flows

Heterogeneous and homogeneous 2.5/3D system connectivity IC package planning and prototyping for evaluating different IC, interposer, package, and PCB integration scenarios.

Provides a complete physical design solution, including flip chip and/or wirebond attach, stacked die, heterogeneous integration, and multi-device System-In-Package (SiP) or modules.

Complete design verification of stacked die assemblies, such as stacked memories, stacked sensor arrays, interposer-based structures, and fan-out wafer-level packaging.