Early prototyping and exploration allows engineers to evaluate different ASIC/chiplet, interposer, package, and PCB integration scenarios in order to meet overall PPA, device size, routability, and
cost goals prior to detailed physical implementation.
Construction and visualization of system-level logical connectivity of multi-die, multi-component, and multi-substrate IC package designs. Provides the ability to use System Verilog and graphical schematics to derive all or partial logical connectivity along with spreadsheet or interactive creation.
Visualization of the complete system in a single floorplan-in-floorplan view with flight lines or data-paths indicating connectivity between devices. Rules-based connectivity optimization can be run from any direction by signal, bus, or interface. Escape and breakout routing can be easily included to drive the System Technology Co-Optimization (STCO) process.
In conjunction with Calibre 3DSTACK, Xpedition Substrate Integrator uniquely identifies geometries per layer per die placement in the assembly, allowing accurate checking between dies. With the ability to differentiate the layers of interest per individual die placement, Calibre 3DSTACK enables designers to verify the physical attributes of each die.
These tools allowed us to detect out-of-sync connectivity between the design intent and the design implementation, preventing potential opens/shorts that could have occurred between the package and the PCB. If undetected, these errors could have created a costly time-consuming respin.