Overview
Calibre® PERC™
The Calibre PERC platform is the industry leader for reliability verification solutions, enabling a vast range of IC circuit reliability checks that are not possible with traditional physical verification tools.
Get in touch with our technical team: 1-800-547-3000
Comprehensive reliability verification
The Calibre PERC reliability platform automatically combines netlist and layout information to perform targeted electrical checks that consider the context of the design intent for both layout-related and circuit-dependent checks.
Foundry Rule Decks
Understanding the foundry view of reliability on your design is necessary for a comprehensive reliability verification strategy. Foundry qualified and supported rule decks are essential to establishing this reliability baseline, not only to guide improvements, but also to establish best practices with internal and 3rd party IP through full-chip sign-off.
Electrostatic Discharge Solutions
When verifying the robustness of your electrostatic discharge (ESD) protection strategy in your design, it is essential to ensure sufficiently-sized devices and interconnect are where they need to be. Understanding the performance of these critical design elements requires a combination of topology, layout and interconnect robustness capabilities in a context-aware environment.
Context-Aware Verification
Target verification rules with precision by leveraging rule deck defined circuit structures in the schematic or layout. Being able to identify the absence of required circuit elements, such as protection devices or level-shifters, is of equal importance. Find your way through the unique complexities of each design with context-aware verification.
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Calibre Consulting Services
We help you adopt, deploy, customize and optimize your complex design environments. Direct access to engineering and product development lets us tap into deep domain and subject matter expertise.
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Design with Calibre blog
Across all process nodes and design styles, the Calibre toolsuite delivers accurate, efficient, comprehensive IC verification and optimization, while minimizing resource usage and tapeout schedules.