Aprisa digital implementation solution

Designing at advanced process nodes requires a new place-and-route paradigm to manage the increasing complexity. Aprisa is a detail-route-centric physical design platform for the modern SoC.

Get in touch with our technical team1-800-547-3000

Key features

Place-and-route technology for complex SoC designs

Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime.


Detail-route-centric architecture

Enables efficient communication between placement optimization, CTS optimization, and detail routing for improved quality-of-results, fewer iterations and 2x faster design convergence.


Leading foundry certified for advanced nodes

Native color-aware MPT routing, sibling routing, congestion-aware low-resistance routing and IR-aware and EM-aware place-and-route innovations deliver highest quality of results.


PowerFirst place-and-route

Focuses on low power as a primary design target while meeting timing constraints. Path-based timing analysis and optimization, low power CTS, and dynamic power-driven P&R help meet goals of modern SoCs.

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