Aprisa Place-and-Route

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Overview

Aprisa Place-and-Route

Designing at advanced process nodes requires a new place-and-route paradigm to manage the increasing complexity. Aprisa is a route-centric physical design platform for the modern SoC.


Get in touch with our technical team1-800-547-3000

An image of the Aprisa place-and-route tool architecture
Key features

Place-and-route technology for complex SoC designs

Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. The detailed-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime.

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Fewer iterations

Detailed-Route-Centric Architecture

<p>The detailed-route-centric architecture enables efficient and frequent communication between placement optimization, CTS optimization, and detailed routing for improved quality-of-results, reduced iterations, and 2X faster design convergence than the competition.</p>

Abstract technological images with code, a fingerprint and lines with connection nodes

Highest quality of results

Specialized for Advanced Nodes

<p>Leading foundry certified for advanced nodes. Innovative technologies, such as native color-aware MPT routing, Sibling Routing, congestion-aware low-resistance routing, and IR-aware and EM-aware place-and-route help to mitigate design challenges and deliver highest quality of results at advanced nodes. </p>

Rainbow colors on a silicon wafer

Low power

PowerFirst Place-and-Route for Low Power

<p>The PowerFirst place-and-route methodology ensures that low power is considered as a primary design target while meeting timing constraints. Advanced technologies such as path-based timing analysis and optimization, low power CTS, and dynamic power-driven P&amp;R, help to meet the demanding low power requirement of modern SoCs.</br></br></p>

Close up of an IC with layers

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