Aprisa digital implementation is an RTL2GDSII solution that offers complete synthesis and place-and-route functionality for top-level hierarchical designs and block-level implementation. It's tapeout quality correlation with signoff tools, both for STA timing and DRC, reduces design closure and ensures optimal performance, power and area (PPA).
Aprisa delivers optimal PPA out-of-the-box. This helps physical designers reduce the effort at each step of the place-and-route flow and achieve faster time-to-market
Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. Its detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results (QoR) at a competitive runtime.
A unified data model brings real route information and parasitics to any engine and step in the flow. Designers can confidently know their design's achievable PPA at pre-route stage, greatly reducing full-flow iterations
Expert designer quality macro placement at a fraction of the time and effort that it would take an experienced designer. Eliminates the need for full-flow iterations to lock down the optimal macro placement for a given design
Target low power as a primary design metric for power sensitive designs, without sacrificing performance. Designers choose the tradeoffs that meet their optimal PPA, reducing power cleanup on the last mile of the design tapeout
Whether physical designers are looking to implement highly complex designs or to tapeout in the shortest amount of time, Aprisa operates mostly out-of-the-box to deliver the PPA and design metrics that matter most, for any given digital IC design project.