Aprisa Place-and-Route

{"showBreadcrumbs":true,"breadcrumbs":[{"title":"Siemens EDA Software","path":"/en-US/"},{"title":"IC Tool Portfolio","path":"/en-US/ic"},{"title":"Aprisa ","path":""}],"tagline":"Overview","title":"Aprisa Place-and-Route","description":"Designing at advanced process nodes requires a new place-and-route paradigm to manage the increasing complexity. Aprisa is a route-centric physical design platform for the modern SoC.","pricingCurrency":"US$","image":{"url":"//images.ctfassets.net/17si5cpawjzf/4bz1Ow4KIxtnZWE6xJpThr/13aae8259acfe15a34dd1a3d7faae948/L4-aprisa-offer-image-640x480.jpg?w=640","alt":"An image of the Aprisa place-and-route tool architecture","linkData":"{\"name\":\"Aprisa-product-thumbnail-640x480\",\"id\":\"4bz1Ow4KIxtnZWE6xJpThr\",\"contentType\":\"image/jpeg\"}"},"phoneIcon":true,"moreInformation":"Get in touch with our technical team1-800-547-3000"}
Overview

Aprisa Place-and-Route

Designing at advanced process nodes requires a new place-and-route paradigm to manage the increasing complexity. Aprisa is a route-centric physical design platform for the modern SoC.


Get in touch with our technical team1-800-547-3000

An image of the Aprisa place-and-route tool architecture
Key features

Place-and-route technology for complex SoC designs

Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. The detailed-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime.

Fewer iterations

Detailed-Route-Centric Architecture

The detailed-route-centric architecture enables efficient and frequent communication between placement optimization, CTS optimization, and detailed routing for improved quality-of-results, reduced iterations, and 2X faster design convergence than the competition.

Highest quality of results

Specialized for Advanced Nodes

Leading foundry certified for advanced nodes. Innovative technologies, such as native color-aware MPT routing, Sibling Routing, congestion-aware low-resistance routing, and IR-aware and EM-aware place-and-route help to mitigate design challenges and deliver highest quality of results at advanced nodes.

Low power

PowerFirst Place-and-Route for Low Power

The PowerFirst place-and-route methodology ensures that low power is considered as a primary design target while meeting timing constraints. Advanced technologies such as path-based timing analysis and optimization, low power CTS, and dynamic power-driven P&R, help to meet the demanding low power requirement of modern SoCs.

Screen shots of the Aprisa place-and-route system.

Ready to talk to someone today?

We're standing by to answer your questions.

Email us

Get in touch with our sales team 1-800-547-3000 or 1-503-685-8000

image of arrows

Join the IC Design Community

Join the discussion on new topics, features, content, and technical experts.

two squares on top of each other

Training and support

Access detailed user application notes, training resources and more.

EDA Consulting

Helping you achieve maximum business impact by addressing your complex technology and enterprise challenges with a unique blend of development experience, design knowledge, and methodology expertise.

{"desc":"This site uses cookies in order to improve your user experience and to provide content tailored specifically to your interests. Detailed information on the use of cookies on this website is provided in our Privacy Policy. You can also manage your preferences there. By using this website, you consent to the use of cookies.","learnMoreText":"Learn More","learnMoreUrl":"https://new.siemens.com/global/en/general/cookie-notice.html","okText":"OK"}