Aprisa Digital Implementation Solution

Designing at advanced process nodes requires a new place-and-route paradigm to manage the increasing complexity. Aprisa is a detail-route-centric physical design platform for the modern SoC.

Get in touch with our technical team1-800-547-3000

Key features

Place-and-route technology for complex SoC designs

Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime.

Fewer iterations

Detail-route-centric architecture

The detail-route-centric architecture enables efficient and frequent communication between placement optimization, CTS optimization, and detail routing for improved quality-of-results, reduced iterations, and 2X faster design convergence than the competition.

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Highest quality of results

Specialized for advanced nodes

Leading foundry certified for advanced nodes. Innovative technologies, such as native color-aware MPT routing, sibling routing, congestion-aware low-resistance routing, and IR-aware and EM-aware place-and-route help to mitigate design challenges and deliver highest quality of results at advanced nodes.

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Low power

PowerFirst place-and-route for low power

The PowerFirst place-and-route methodology ensures that low power is considered as a primary design target while meeting timing constraints. Advanced technologies such as path-based timing analysis and optimization, low power CTS, and dynamic power-driven P&R, help to meet the demanding low power requirement of modern SoCs.

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