Tessent Test Solutions

Delivers the highest quality deterministic scan test with the lowest manufacturing test cost, using patented on-chip compression to reduce test data volume and cut test time.

Automates the generation and insertion of IEEE 1838-compliant hardware and defines the IEEE test access architecture for 3D stacked integrated circuits.

Enables comprehensive automation and integration of test, repair, debug, and characterization of embedded memories.

Enables ISO 26262 compliance and is the ideal logic built-in self test solution for safety-critical devices such as ICs used in automotive and medical applications.

Reduces DFT development time and manufacturing test cost by decoupling core-level and chip-level DFT requirements.

Reduces DFT implementation effort with an optimal automation of the Tessent Shell flow for hierarchical DFT.

Provides automation and integration for IEEE 1687 IJTAG compliant test and instrumentation IP from various sources into an IC design.

Combines automation and on-chip IP to enable IC test and diagnosis at any point during a vehicle’s functional operation – a fundamental requirement of the ISO 26262 standard.

Improves test compression levels up to 4X, enables hierarchical DFT, logic BIST readiness, and scan insertion.

Simplifies the process of generating high-coverage compact test sets. Its ability to be applied to most any type of design makes it the most versatile ATPG solution available.

Automates adding IEEE 1149.1 standard boundary scan support to ICs of any size or complexity, reducing development effort and improving time-to-market.

Simulates transistor-level defects for analog, mixed-signal, and non-scan digital circuits. It automates coverage assessment to help meet quality standards such as ISO 26262.

Applies layout-aware and cell aware diagnosis technologies to accurately classify and identify the location of defects causing failures during manufacturing test.

Accelerates test bring-up, debug, and silicon characterization of devices containing Tessent ATPG, EDT, BIST, and/or IJTAG test structures within an automated interactive environment.

Eliminates noise from diagnosis data to determine the underlying root causes, identify systematic yield limiters, and select the best devices for failure analysis.