Best of Tessent at International Test Conference

Tomonori Sasaki with Digital Design Technology at Renesas Electronics Corp. presents their strategy to identify causes of failure analysis.

Hiroyuki Iwata, Digital Design Technology at Renesas Electronics Corp. discusses the challenges of DFT for heterogenous security operations center (SoC) design.

Saket Goyal, ASIC product division, Broadcom, shares his experience with Tessent SSN on 3D integrated circuit (IC) designs.

Thomas Zanon, Yield Management Solutions Engineer, PDF Solutions, discusses a collaborative solution to yield learning.

Arm and Siemens developed a solution for handling embedded MRAM technology. This paper explores ECC-aware test/repair technology: MBIST functionality to make in-system, user-programmable trade-offs on eMRAM repair resources.

SSN provides many advantages by using a packetized scan data delivery network. This presentation shows four types of clock generation that can be selected for SSN, and the tradeoffs and benefits of each.

The adaptive nature of SSN makes it possible to change the selection of cores tested in parallel and which patterns to use. Read this paper to learn more.

The Veloce hardware was fully designed by Siemens including huge SoC that faces many of the SoC design challenges our customers face. This presentation describes how SSN was implemented as a simple solution to their challenges.

Learn more about the efficiency of packetized data delivery in 2.5D/3D designs in this technical presentation.

Tessent LogicBIST observation scan technology (OST) has been shown to improve test time by 5x. This presentation shows some new features that enable OST to work in the presence of unknown/X states. 

Integration with leading tester companies includes automation such that multiple failing identical cores are identified and automatically tested so each can have a full diagnosis run.

SSN provides packetized data to cores, separating the core scan channel needs from the size of scan delivery bus and IO pins. This talk shows new Fast IO for SSN that allows it to run at even higher frequencies. 

This presentation describes features in the newly released RTL Pro including test point identification, wrapper identification, rules, checks and more.

Geir Eide explains how providing visibility into the real-world behavior of large SoCs can result in faster time to market, lower development costs and better performance overall.

Arm presents on BIST features for multi-port register files and the types of faults detected.

This presentation highlights how Silicon Insight can connect to Salland’s DTX bench instrument, which provides a high speed and density option to your device bring-up equipment.

We demonstrate 50% faster turnaround times for volume scan diagnosis workloads on Amazon Web Services (AWS) cloud compared to on-premises.

Implementing DFT techniques is a necessity to achieve high-quality chips. With the ever-growing complexity of designs, the effort to efficiently test these designs is also growing.

Packetized scan data delivery is a trending common practice for efficient delivery of test-pattern data. This poster explains four clocking techniques.

Learn how better test time and coverage are achieved with OST in this poster.

With the growing complexity of integrated circuits, packetized scan data has shown to be a major component in test time reduction.

Concurrent read and write operations performed in the same row - or even at the same address - allow testing for all possible combinations of two aggressors on a victim word line or bit line without increasing test time.

This poster presents how EDA can facilitate accurate MBIST setup of the design with Shared Bus interface and consequently reduce the turnaround time.

It's possible to insert all major DFT components at RTL. This leaves only scan insertion and shared wrapper cell logic to be inserted at the gate level, making shift-left a reality.