Tessent DefectSim is a transistor-level defect simulator for analog, mixed-signal (AMS), and non-scan digital circuits. It measures defect coverage and defect tolerance and is perfect for both high-volume and high-reliability ICs.
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Tessent DefectSim replaces manual test coverage assessment in AMS circuits, generating objective data to guide improvements needed to meet quality and functional safety standards and test coverage goals.
<p>Tessent DefectSim builds on the transistor-level defect-injection techniques used in TestKompress Cell-Aware ATPG for scannable digital circuits. Tessent DefectSim is suitable for industrial circuit blocks containing hundreds or hundreds of thousands of transistors, and DC, AC, or transient analysis. </p>
<p>Tessent DefectSim generates an executive summary listing likelihood-weighted defect coverage and the confidence interval. The summary also includes a matrix that lists each defect and whether it was detected by a failing test limit or a digital output differing from the defect-free circuit’s output. A second summary reports all ISO 26262 metrics.</p>
<p>Tessent DefectSim uses many techniques to dramatically reduce total simulation time compared to simulating production tests and flat-extracted layout netlists in classic SPICE on parallel CPUs. Reduces total simulation time up to one million times compared to simulating a production test for each possible defect in a flat netlist.</p>
"We evaluated Tessent DefectSim on several automotive ICs and concluded it is a highly-automated and flexible solution that guides improvements in test and design-for-test techniques and allows us to measurably improve the defect coverage of analog tests."
Wim Dobbelaere, Director of test and product engineering, ON Semiconductor
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