Improve AMS Safety, Test Quality, and Time. Tessent DefectSim replaces manual test coverage assessment in AMS circuits, generating objective data to guide improvements needed to meet quality and functional safety standards and test coverage goals.
Built on the transistor-level defect-injection techniques used in TestKompress Cell-Aware ATPG for scannable digital circuits, DefectSim is suitable for industrial circuit blocks containing hundreds or thousands of transistors.
Generate an executive summary listing likelihood-weighted defect coverage, confidence interval, and a matrix listing each defect and whether it was detected by a failing test limit or a digital output.
Dramatically reduce total simulation time compared to simulating production tests and flat-extracted layout netlists in classic SPICE on parallel CPUs.