Tessent TestKompress

Overview
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Overview

Tessent TestKompress

Tessent TestKompress delivers the highest quality embedded deterministic scan test with the lowest manufacturing test cost. It uses a patented on-chip compression technique to create scan pattern sets that have dramatically less test data volume and reduced test time on the automatic test equipment.

Get in touch with our technical team: 1-800-547-3000

Illustration of embedded test compression | Tessent TestKompress delivers the highest quality embedded deterministic scan test with the lowest manufacturing test cost.

Tessent TestKompress Resources

Key Features

Industry-Leading Scan Test Tool

Tessent TestKompress uses Embedded Deterministic Test technology to achieve the highest
level of test quality while compressing scan patterns often 100X or more.

Quality

Highest Defect Coverage

Tessent TestKompress supports all traditional fault models used for uncovering both static and dynamically activated defects. Support for user-defined fault models (UDFM) also allows virtually any defect mechanism to be modeled and targeted.

Abstract image showing a cityscape rising from an IC chip | Tessent IC test solutions

Productivity

Fully Automated

Tessent TestKompress is built on the Tessent Connect end-to-end automation platform, which offers comprehensive automation, TCL-based scripting, and introspection capabilities. To maximize throughput, automatic test pattern generation (ATPG) can be distributed across multiple processors.

Stylized IC "cityscape" with bitcode rays emanating upwards | Tessent ScanPro is integrated into the end-to-end automation flow of Tessent Connect and includes advanced design introspection and editing capabilities.

Efficiency

Lower Test Time and Pattern Count

Built on the patented Embedded Deterministic Test (EDT) technology, Tessent TestKompress reduces both test time and pattern volume by several orders of magnitude without any loss in fault coverage.

IC schematics with light bursts | Tessent ScanPro includes the VersaPoint test point technology that directly targets ATPG pattern volume reduction of 2X to 4X in addition to increasing logic BIST test coverage.

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