Tessent TestKompress uses Embedded Deterministic Test technology to achieve the highest
level of test quality while compressing scan patterns often 100X or more.
Tessent TestKompress supports all traditional fault models used for uncovering both static and dynamically activated defects. Support for user-defined fault models (UDFM) also allows virtually any defect mechanism to be modeled and targeted.
Tessent TestKompress is built on the Tessent Connect end-to-end automation platform, which offers comprehensive automation, TCL-based scripting, and introspection capabilities. To maximize throughput, automatic test pattern generation (ATPG) can be distributed across multiple processors.
Built on the patented Embedded Deterministic Test (EDT) technology, Tessent TestKompress reduces both test time and pattern volume by several orders of magnitude without any loss in fault coverage.
Tessent Silicon Lifecycle solutions provide IP and applications that detect, mitigate and eliminate risks throughout the IC lifecycle, from DFT through continuous IC monitoring.
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Helping you achieve maximum business impact by addressing complex technology and enterprise challenges with a unique blend of development and design experience and methodology expertise.