Tessent Advanced DFT

Tessent BoundaryScan

Tessent BoundaryScan is a complete solution for automated generation and integration of on-chip test infrastructure, boundary scan, and test access port.

Why Tessent BoundaryScan?

Tessent BoundaryScan logic can be accessed throughout the life of the IC, including manufacturing test at all package levels, silicon debug, and system verification to detect defects before shipment, reducing field support costs and increasing customer satisfaction.

Complete boundary scan and TAP controller integration

Automatically generates and integrates RTL code for the TAP controller and boundary scan cells into the design RTL. Generates scripts for logic synthesis, simulation testbenches and test patterns for manufacturing test.

Supports multiple formats

Tessent Boundary scan supports IEEE 1149.1 custom boundary scan cells and contactless I/O test and has an option for 1149.6 boundary scan support.

IEEE 1687 IJTAG interoperability

Automatically connects IJTAG networks and instruments to the newly inserted TAP controller and generates resulting Instrument Connectivity Language files. I/O tests are generated in Procedural Description Language (PDL) format.

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