Tessent MemoryBIST includes a uniquely comprehensive automation flow that provides design rule checking, test planning, integration, and verification all at the RTL or gate level.
The advanced BAP provides a configurable interface to optimize in-system testing. It supports a low-latency protocol to configure the memory BIST controller, execute Go/NoGo tests, and monitor the pass/fail status. Test time can be significantly reduced by eliminating shift cycles to serially configure the controllers in the IJTAG environment.
Memory test algorithms—either custom or chosen from a library—can be hardcoded into the Tessent MemoryBIST controller, then applied to each memory through run-time control. This lets you select shorter test algorithms as the manufacturing process matures. The Tessent MemoryBIST Field Programmable option includes full run-time programmability.
The Tessent MemoryBIST repair option eliminates the complexities and costs associated with external repair flows. It tests and permanently repairs all defective memories in a chip using virtually no external resources. The Tessent MemoryBIST built-in self-repair (BISR) architecture uses programmable fuses (eFuses) to store memory repair info.
Tessent Silicon Lifecycle solutions provide IP and applications that detect, mitigate and eliminate risks throughout the IC lifecycle, from DFT through continuous IC monitoring.
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