Tessent MemoryBIST

Tessent MemoryBIST provides a complete solution for at-speed test, diagnosis, repair, debug, and characterization of embedded memories. Leveraging a flexible hierarchical architecture, built-in self-test and self-repair can be integrated in individual cores as well as at the top level.

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Key features

Industry-Leading Memory Built-in Self-Test

Tessent MemoryBIST includes a uniquely comprehensive automation flow that provides design rule checking, test planning, integration, and verification all at the RTL or gate level.

Advanced BIST Access Port

The advanced BAP provides a configurable interface to optimize in-system testing. It supports a low-latency protocol to configure the memory BIST controller, execute Go/NoGo tests, and monitor the pass/fail status. Test time can be significantly reduced by eliminating shift cycles to serially configure the controllers in the IJTAG environment.

Stylized ICs | Tessent IC test solutions

Algorithm Programmability

Memory test algorithms—either custom or chosen from a library—can be hardcoded into the Tessent MemoryBIST controller, then applied to each memory through run-time control. This lets you select shorter test algorithms as the manufacturing process matures. The Tessent MemoryBIST Field Programmable option includes full run-time programmability.

Stylized IC "cityscape" with bitcode rays emanating upwards | Tessent ScanPro is integrated into the end-to-end automation flow of Tessent Connect and includes advanced design introspection and editing capabilities.

Power-Aware On-Chip Self-Repair

The Tessent MemoryBIST repair option eliminates the complexities and costs associated with external repair flows. It tests and permanently repairs all defective memories in a chip using virtually no external resources. The Tessent MemoryBIST built-in self-repair (BISR) architecture uses programmable fuses (eFuses) to store memory repair info.

IC schematics with light bursts | Tessent ScanPro includes the VersaPoint test point technology that directly targets ATPG pattern volume reduction of 2X to 4X in addition to increasing logic BIST test coverage.

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