Tessent Streaming Scan Network packetizes test data to dramatically reduce DFT implementation effort and reduce manufacturing test cost. By decoupling core-level and chip-level DFT requirements, each core can be designed with the most optimal compression configuration for that core.
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Tessent Streaming Scan Network delivers the promise of true hierarchical plug-n-play DFT. By decoupling core-level DFT configuration from chip level DFT resources, the DFT planning and implementation effort is dramatically reduced while simultaneously reducing manufacturing test cost.
Minimize DFT Effort
With Tessent Streaming Scan Network, core and chip level DFT is completely decoupled. Core-level compression can be optimized without considering other cores or chip level resources. Decisions such as core grouping are made during pattern re-targeting rather than design time.
By eliminating top-level test mode muxing and routing of DFT signals from chip level pins to each core, routing and timing closure of DFT signals is dramatically simplified. Streaming Scan Network is ideal for tile-based design with abutment.
Reduce Test Costs
There is no need to compromise manufacturing test cost. Streaming Scan Network data packets contain 100 payloads. By combining automatic bandwidth tuning and local generation of DFT signals, whitespace is virtually eliminated from the test data. Identical cores can be tested at constant cost, with diagnosis support.
"With Tessent Streaming Scan Network technology, we are able to offer our customers a scalable test access solution ideal for today’s and tomorrow’s advanced IC designs. SSN significantly reduces the effort needed to make complex designs highly testable."
Sangyun Kim, Vice President of Design Technology Team , Samsung Electronics
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