Tessent Test Solutions

Tessent In-System Test provides the embedded hardware and necessary software to enable application of high-quality deterministic test patterns while reducing test time as compared to traditional logic BIST.

Deliver the highest quality deterministic scan test with the lowest manufacturing test cost, using patented on-chip compression to reduce test data volume and cut test time.

Automate the generation and insertion of IEEE 1838-compliant hardware and define the IEEE test access architecture for 3D stacked integrated circuits.

Reduce DFT development time and manufacturing test cost by decoupling core-level and chip-level DFT requirements with Tessent Streaming Scan Network (SSN).

Enable comprehensive automation and integration of test, repair, debug, and characterization of embedded memories with Tessent MemoryBIST.

Enable ISO 26262 compliance with the ideal logic built-in self-test solution for safety-critical devices such as ICs used in automotive and medical applications.

Combine automation and on-chip IP to enable IC test and diagnosis at any point during a vehicle’s functional operation – a fundamental requirement of the ISO 26262 standard.

Reduce DFT implementation effort with an optimal automation of the Tessent Platform flow for hierarchical DFT.

Improve test compression levels up to 4X, enable hierarchical DFT, logic BIST readiness and scan insertion with Tessent ScanPro.

Streamline a broad array of critical DFT tasks with this new software developed for IC design teams.

Simplify the process of generating high-coverage compact test sets. The ability of Tessent FastScan to be applied to most any type of design makes it the most versatile ATPG solution available.

Provide automation and integration for IEEE 1687 IJTAG compliant test and instrumentation IP from various sources into an IC design.

Automate the addition of IEEE 1149.1 standard boundary scan support to ICs of any size or complexity, reducing development effort and improving time-to-market.

Simulate transistor-level defects for analog, mixed-signal and non-scan digital circuits, automating coverage assessment to help meet quality standards such as ISO 26262.