Tessent Streaming Scan Network (SSN) wins Siemens Innovator of the Year 2022 for Outstanding Invention. SSN enables chip designers to easily implement the silicon test architecture that drastically reduces silicon test time and test cost. Watch video to learn more.
The Tessent Streaming Scan Network (SSN) technology eliminates the difficult and costly trade-offs between test implementation effort and manufacturing test cost by decoupling core-level and chip-level DFT requirements.
Built on the foundation of the best-in-class solutions for each test discipline, Tessent logic and memory test product brings all the capabilities together in a powerful test flow that ensures total chip coverage.
Access the ITC presentations from Tessent technologists, customers, and partners from this page. Along with its associated workshops and tutorials, ITC is the best place to discover new technologies for DFT, IC test, yield learning and in-life monitoring and analytics.
Decrease time to yield, manage manufacturing excursions and recover yield caused by systematic defects. By understanding how to manage and optimize the test and data collection environment, yield learning solutions can be setup to identify systematic defects that cause low yield, saving time.