The Siemens 3D IC Reliability workflow includes comprehensive analysis tools for use during planning, implementation through signoff to ensure advanced SiP designs meet product’s quality, yield, manufacturability, and reliability requirements. The 3D IC Reliability workflow complements Siemens 3D IC designer, architect, analysis and test workflows.
An integrated, gate/transistor level thermal analysis engine enables IC designers to collaborate with system and package designers to evaluate the thermal implications of their chiplets in the context of the entire SiP design. Create Boundary Condition Independent Reduced Order Model (BCI-ROM) thermal models to support full SiP, PCB and system-level thermal analysis. Use thermo-mechanical stress analysis to assess stress-induced reliability issues during package assembly and thermal cycling during production operation. Leverage advanced design for manufacturing (DFM) checking tools for package and chiplet designs to ensure optimal product yield and reliability.
