Advanced 3D IC Design Flow
3D IC design and packaging solutions
An integrated IC packaging solution that covers everything from planning and prototyping to signoff for various integration technologies such as FCBGA, FOWLP, 2.5/3DIC, and others. Our 3D IC packaging solutions help you overcome the limitations of monolithic scaling.
What is 3D IC design?
The semiconductor industry has made great strides in ASIC technology over the last 40 years, leading to better performance. But as Moore's law nears its limits, scaling devices is becoming harder. Shrinking devices now takes longer, costs more, and presents challenges in technology, design, analysis, and manufacturing. Thus, enters 3D IC.
What’s driving 2.5/3D IC?
3D IC is a new design paradigm driven by the diminishing returns of IC technology scaling, AKA Moore’s Law.
Cost-yield driving alternatives to monolithic solutions
Alternatives include the breakdown of a System-on-Chip (SOC) into smaller sub-functions or components known as "chiplets" or "hard IP,” and the use of multiple dies to overcome the limitations imposed by the size of a reticle.
Higher bandwidth / lower power
Achieved by bringing memory components closer to the processing units, reducing the distance and latency in accessing data. Components can also be stacked vertically, allowing for shorter physical distances between them.
Heterogeneous integration
There are several advantages to heterogeneous integration, including the ability to mix different process and technology nodes, as well as the ability to leverage 2.5D/3D assembly platforms.
3D IC design solutions
Our 3D IC design solutions support architectural planning/analysis, physical design planning/verification, electrical and reliability analysis, and test/diagnostic support through manufacturing handoff.
Heterogeneous 2.5/3D integration
A full-system for heterogeneous system planning, offering flexible logic authoring for seamless connectivity from planning to final system LVS. Floorplanning functionality supports scaling complex heterogeneous designs.
3D SoIC implementation
Achieve faster design cycle times and path to tapeout with design routability and PPA closure during placement optimization. In-Hierarchy-Optimization ensures top-level timing closure. Optimized design specs deliver better PPA, certified for TSMC advanced nodes.
Substrate implementation
A single platform supports advanced SIP, chiplet, silicon interposer, organic, and glass substrate design, reducing design time with an advanced IP reuse methodology. In-design compliance checking for SI/PI and process rules eliminates analysis and sign-off iterations.
Functional verification
This solution verifies the package assembly netlist against a "golden" reference netlist to ensure functional correctness. It uses an automated workflow with formal verification, checking all interconnections between semiconductor devices in minutes, ensuring high accuracy and efficiency.
Electrical simulation & sign-off
Drive physical layout with in-design analysis and electrical intent. Combine silicon/organic extraction for SI/PI simulation with technology-accurate models. Enhance productivity and electrical quality, scaling from predictive analysis to final sign-off.
Thermal/mechanical simulation
Thermal solution covering transistor to system-level and scales from early planning to system sign-off, for detailed die-level thermal analysis with accurate package and boundary conditions. Reduce cost by minimizing the need for test chips and helps identify system reliability issues.
.png?auto=format,compress)
Product lifecycle management
ECAD-specific library and design data management. Ensures WIP data security and traceability, with component selection, library distribution and model reuse. Seamless PLM integration for product lifecycle management, manufacturing coordination, new part requests and asset management.
2.5D/3D design-for-test
Handle multiple die/chiplets through die-level and stack-level testing, supporting IEEE standards like 1838, 1687, and 1149.1. It provides full access to die in-package, wafer test validation and extends 2D DFT to 2.5D/3D, using Tessent Streaming Scan Network for seamless integration.
Verification IP for 3D IC
Eliminate time spent developing and maintaining custom bus functional models (BFMs) or verification components. Avery Verification IP (VIP) enables System and System-on-Chip (SoC) teams to achieve dramatic verification productivity improvements.
3D IC design & verification
The Solido Intelligent Custom IC Platform, powered by proprietary AI-enabled technology, offers leading-edge circuit verification solutions designed to address 3D IC challenges, meet stringent signal, power and thermal integrity requirements and accelerate development.
Design for reliability
Ensure interconnect reliability and ESD resilience with comprehensive point-to-point (P2P) resistance, and current density (CD) measurements across the die, interposer, and package. Account for process node and ESD methodology differences with robust interconnect between protection devices.
What can 3D IC design solutions do for you?
A chiplet is designed with the understanding it will be connected to other chiplets within a package. Proximity and shorter interconnect distance means less energy consumption, but it also means coordinating a greater number of variables like energy efficiency, bandwidth, area, latency and pitch.
Optimize
Co-optimization for power, performance, area, cost and reliability across silicon, package, interposer, and PCB
Adapt
Empower design engineers with accessible technologies that reduces dependency on experts
Collaborate
Scalability to manage and communicate heterogenous data across enterprise-wide teams and maintain digital continuity
Minimize
Eliminate iterations through early insight into downstream performance and process effects through continuous verification
Frequently asked questions about our 3D IC Solutions
3D IC is a new design paradigm driven by the diminishing returns of IC technology scaling, AKA Moore’s Law. 3D IC leverages new advanced packaging technologies that enable the integration of one or more chiplets into a single package. Chiplets are integrated circuits (IC) optimized for integration into a single package.
3D IC designs require the seamless integration of multi-domain ECAD/MCAD tools within a highly integrated, design platform, referred to as 3D IC workflows. Leveraging Siemens’ broad portfolio of leading EDA and MCAD tools, a comprehensive set of workflows are offered spanning the spectrum from system level decomposition to manufacturing handoff to empower its customers to design these complex, chiplet-based designs.
The 3D IC workflows also require tight integration with a comprehensive set of design kits to enable the design, integration, and assembly of chiplet-based 3D IC designs. To enable a chiplet ecosystem, Siemens has taken leadership in driving the new CDX/OCP 3D IC Design Kits (3DK) initiatives in collaboration with other EDA vendors. Siemens is sponsoring and actively driving the adoption of these new industry standards by the JEDEC industry standards body and is committed to formally adopt these new standards in its tools and workflows.
3D IC technology enables a system-based approach to decompose an electronic system or subsystem into a chiplet based system in package (SiP) design which offers increased performance, lower cost, reduced form factor and more flexible, cost-effective product variants.
The Siemens 3D IC workflows support architectural planning/analysis, physical design planning/verification, electrical and reliability analysis, and test/diagnostic support through manufacturing handoff.
The workflows integrate and back-annotate the electrical/reliability analysis results into the design planning/implementation tools enabling designers to run early predictive, in-design, and sign-off analysis. This new predictive analysis capability provides designers an early look at performance and reliability to facilitate architectural exploration before executing extensive physical design resources. In-design analyses enables design teams to interactively run checks during the design process and make design changes as needed rather than waiting for sign-off checks to be run on completed designs. The signoff checks are run on the final design to ensure functionality, performance, and reliability/manufacturability of the design exemplars before release to manufacturing.
The Siemens 3D IC solutions include five workflows that support architectural planning and analysis, physical design and verification, electrical analysis, reliability analysis and 3D IC Test planning and analysis support. Additionally, an integrated mechanical design and analysis workflow is available to support mechanical package design and system level, thermal/mechanical signoff level analysis. Although Siemens includes all the required tools for the respective workflows, the modular architecture supports the integration of additional best is class and/or incumbent customer tools and workflows.
Siemens offers best in class package planning and 3D stack validation tools in the 3D IC design workflows. The integrated electrical and reliability workflow support early predictive, in-design and signoff analysis of multi-layer 2.5/3D designs. The test workflows facilitate collaboration between the package/chiplet design teams with the DFT/test teams leveraging the best-in-class Siemens multi-die DFT tool suite.
3D IC technology offers the system designer nearly unlimited flexibility to partition their design into chiplets each optimized in an IC technology node best suited for each function. The architectural planning and design workflows facilitate collaboration between the system/RTL design teams with the package/chiplet design teams leveraging predictive analysis to efficiently home in on an optimal architecture prior to deploying expensive and time-consuming design implantation on potentially non-optimal or pathological design.
In-design analysis enables the physical design and electrical/reliability analysis teams to validate the design during the implementation phases, catching errors prior to signoff checks run on completion of the physical design thus avoiding rework and related schedule delays.
Careful, up front and validated DFT/test workflow enable timely test bring up during the new product introduction (NPI) phase of the program enabling earlier entry to market of semiconductor products.