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3D IC Workflow Solutions

Siemens 3D IC Architect: STCO architectural exploration

The Siemens 3D IC Architect workflow solution enables STCO architectural exploration and predictive analysis to develop optimal 2.5D and 3D IC package designs.

3D IC Architect Workflow

What is Siemens 3D IC Architect Workflow?

The Siemens 3D IC Architect workflow enables system technology co-optimization (STCO) architectural exploration and predictive analysis. The 3D IC Architect workflow complements Siemens 3D IC designer, analysis, reliability and test workflows.

The 3D IC Architect workflow enables system and RTL designers to rapidly capture viable design architectures of design scenarios, including chiplet components and standard die-to-die (D2D) interfaces, using a library of generic connectivity IP models.

Evaluating multiple design scenarios enables the system designer to collaborate with the package design leads to assess the power, performance, area (PPA) and cost attributes early in the design. By leveraging predictive modeling and analysis workflows during the planning process, teams can determine optimal heterogeneous design architectures before initiating the detailed design implementation process.

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Key Capabilities of Siemens 3D IC Architect Workflow

Questa VIP 2.5D Parts

  • Generic library of die-to-die (D2D) interfaces and chip-to-chip (C2C) connectivity IP
  • System Verilog Functional models and test benches
  • D2D Connectivity Configuration
  • D2D/C2C IP Mapping

Architectural Planning

  • Package technology/stacking planning
  • SiP level chiplet placement
  • Internal/External high speed IO planning
  • Logical Equivalence Checking (LEC)

Predictive Analysis

  • Early D2D signal integrity planning and analysis
  • Early power delivery network planning and analysis
  • Early thermal planning and analysis
  • Early mechanical stress planning and analysis

Benefits of the Siemens 3D IC Architect Workflow

  • Enables STCO architectural exploration and predictive analysis
  • Supports technology mapping and connectivity of high speed internal and external interface IP
  • Facilitates collaboration between system/RTL architects and package lead
Hand in latex gloves holding a 3D IC chip