The Siemens 3D IC Architect workflow enables system technology co-optimization (STCO) architectural exploration and predictive analysis. The 3D IC Architect workflow complements Siemens 3D IC designer, analysis, reliability and test workflows.
The 3D IC Architect workflow enables system and RTL designers to rapidly capture viable design architectures of design scenarios, including chiplet components and standard die-to-die (D2D) interfaces, using a library of generic connectivity IP models.
Evaluating multiple design scenarios enables the system designer to collaborate with the package design leads to assess the power, performance, area (PPA) and cost attributes early in the design. By leveraging predictive modeling and analysis workflows during the planning process, teams can determine optimal heterogeneous design architectures before initiating the detailed design implementation process.