Advanced 3D IC Design Flow
3D IC design and packaging solutions
An integrated IC packaging solution that covers everything from planning and prototyping to signoff for various integration technologies such as FCBGA, FOWLP, 2.5/3DIC, and others. Our 3D IC packaging solutions help you overcome the limitations of monolithic scaling.
What is 3D IC design?
The semiconductor industry has made great strides in ASIC technology over the last 40 years, leading to better performance. But as Moore's law nears its limits, scaling devices is becoming harder. Shrinking devices now takes longer, costs more, and presents challenges in technology, design, analysis, and manufacturing. Thus, enters 3D IC.
What’s driving 2.5/3D IC?
3D IC is a new design paradigm driven by the diminishing returns of IC technology scaling, AKA Moore’s Law.
Cost-yield driving alternatives to monolithic solutions
Alternatives include the breakdown of a System-on-Chip (SOC) into smaller sub-functions or components known as "chiplets" or "hard IP,” and the use of multiple dies to overcome the limitations imposed by the size of a reticle.
Higher bandwidth / lower power
Achieved by bringing memory components closer to the processing units, reducing the distance and latency in accessing data. Components can also be stacked vertically, allowing for shorter physical distances between them.
Heterogeneous integration
There are several advantages to heterogeneous integration, including the ability to mix different process and technology nodes, as well as the ability to leverage 2.5D/3D assembly platforms.
3D IC design solutions
Our 3D IC design solutions support architectural planning/analysis, physical design planning/verification, electrical and reliability analysis, and test/diagnostic support through manufacturing handoff.
Heterogeneous 2.5/3D integration
A full-system for heterogeneous system planning, offering flexible logic authoring for seamless connectivity from planning to final system LVS. Floorplanning functionality supports scaling complex heterogeneous designs.
3D SoIC implementation
Achieve faster design cycle times and path to tapeout with design routability and PPA closure during placement optimization. In-Hierarchy-Optimization ensures top-level timing closure. Optimized design specs deliver better PPA, certified for TSMC advanced nodes.
Substrate implementation
A single platform supports advanced SIP, chiplet, silicon interposer, organic, and glass substrate design, reducing design time with an advanced IP reuse methodology. In-design compliance checking for SI/PI and process rules eliminates analysis and sign-off iterations.
Functional verification
This solution verifies the package assembly netlist against a "golden" reference netlist to ensure functional correctness. It uses an automated workflow with formal verification, checking all interconnections between semiconductor devices in minutes, ensuring high accuracy and efficiency.
Electrical simulation & sign-off
Drive physical layout with in-design analysis and electrical intent. Combine silicon/organic extraction for SI/PI simulation with technology-accurate models. Enhance productivity and electrical quality, scaling from predictive analysis to final sign-off.
Thermal/mechanical simulation
Thermal solution covering transistor to system-level and scales from early planning to system sign-off, for detailed die-level thermal analysis with accurate package and boundary conditions. Reduce cost by minimizing the need for test chips and helps identify system reliability issues.
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Product lifecycle management
ECAD-specific library and design data management. Ensures WIP data security and traceability, with component selection, library distribution and model reuse. Seamless PLM integration for product lifecycle management, manufacturing coordination, new part requests and asset management.
2.5D/3D design-for-test
Handle multiple die/chiplets through die-level and stack-level testing, supporting IEEE standards like 1838, 1687, and 1149.1. It provides full access to die in-package, wafer test validation and extends 2D DFT to 2.5D/3D, using Tessent Streaming Scan Network for seamless integration.
Verification IP for 3D IC
Eliminate time spent developing and maintaining custom bus functional models (BFMs) or verification components. Avery Verification IP (VIP) enables System and System-on-Chip (SoC) teams to achieve dramatic verification productivity improvements.
3D IC design & verification
The Solido Intelligent Custom IC Platform, powered by proprietary AI-enabled technology, offers leading-edge circuit verification solutions designed to address 3D IC challenges, meet stringent signal, power and thermal integrity requirements and accelerate development.
Design for reliability
Ensure interconnect reliability and ESD resilience with comprehensive point-to-point (P2P) resistance, and current density (CD) measurements across the die, interposer, and package. Account for process node and ESD methodology differences with robust interconnect between protection devices.
What can 3D IC design solutions do for you?
A chiplet is designed with the understanding it will be connected to other chiplets within a package. Proximity and shorter interconnect distance means less energy consumption, but it also means coordinating a greater number of variables like energy efficiency, bandwidth, area, latency and pitch.
Optimize
Co-optimization for power, performance, area, cost and reliability across silicon, package, interposer, and PCB
Adapt
Empower design engineers with accessible technologies that reduces dependency on experts
Collaborate
Scalability to manage and communicate heterogenous data across enterprise-wide teams and maintain digital continuity
Minimize
Eliminate iterations through early insight into downstream performance and process effects through continuous verification