Siemens' High-Level Synthesis (HLS) and Verification (HLV) platform improves your ASIC and FPGA design and verification flow when compared to traditional RTL. Using C++ or SystemC Catapult delivers leading quality of results for performance, power, and area, in addition to unique HLV solutions.
RTL productivity, especially for new and complex value-add blocks, has stalled. The design and verification challenges of creating new and novel architectures that deliver advantages in silicon for Wireless, 5G, AI/ML, Automotive, or Video/Image processing isn’t making life easier for design teams.
Will your hardware be system performance limited? Did you pick the right fundamental memory architecture? Or did you only find out during system integration? High-Level Synthesis accelerates your design space exploration.
Delivering an optimal balance of Performance, Power and Area for your design needs is hard. Too little performance, too much power or too much area and you might miss a product cycle. Leverage HLS to design better and faster.
Discovering bugs late in RTL means missed opportunities, less competitive silicon, tape out delays and ECO headaches. Catapult HLS design and verification delivers right-first-time RTL designs, with reduced server and tool cost.
The past several years have seen an explosion in the adoption of HLS for chip design driven by increasing design and verification complexity as well as time to market pressures. Catapult HLS enables designers to get their chips to market faster by shortening the overall design and verification flow.
Catapult High-Level Synthesis solutions deliver C++ and SystemC language support, FPGA and ASIC independence, ASIC power estimation and optimization plus the latest in Physically aware multi-VT area and performance optimization to elevate your designs.
Accelerate your High-Level Verification (HLV) flow with known and trusted methods using the Catapult HLV Platform. Reduce your overall SoC verification turnaround time and costs by up to 80% leveraging High-Level Design Checking, Code/Functional Coverage, and static plus formal methods.
Find out how the Catapult High-Level Synthesis and Verification platform enables you to do more, and do it better. Learn about AI/ML, Deep Learning, Computer Vision, Communications, Video, and more. Siemens' High-Level Synthesis and Verification (HLS & HLV) tools deliver the competitive edge you need.