High-Level Synthesis & Verification

Siemens' High-Level Synthesis (HLS) and Verification (HLV) platform improves your ASIC and FPGA design and verification flow when compared to traditional RTL. Using C++ or SystemC Catapult delivers leading quality of results for performance, power, and area, in addition to unique HLV solutions.

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TRENDS & TECHNOLOGIES

RTL Design & Verification is Too Slow & Expensive

RTL productivity, especially for new and complex value-add blocks, has stalled. The design and verification challenges of creating new and novel architectures that deliver advantages in silicon for Wireless, 5G, AI/ML, Automotive, or Video/Image processing isn’t making life easier for design teams.

Architecture Exploration

Will your hardware be system performance limited? Did you pick the right fundamental memory architecture? Or did you only find out during system integration? High-Level Synthesis accelerates your design space exploration.

Catapult your design

Optimal Power Performance and Area

Delivering an optimal balance of Performance, Power and Area for your design needs is hard. Too little performance, too much power or too much area and you might miss a product cycle. Leverage HLS to design better and faster.

Optimize your PPA

Are You Still Debugging RTL?

Discovering bugs late in RTL means missed opportunities, less competitive silicon, tape out delays and ECO headaches. Catapult HLS design and verification delivers right-first-time RTL designs, with reduced server and tool cost.

Find bugs faster with HLS

Catapult High-Level Synthesis Solutions

Catapult High-Level Synthesis solutions deliver C++ and SystemC language support, FPGA and ASIC independence, ASIC power estimation and optimization plus the latest in Physically aware multi-VT area and performance optimization to elevate your designs.

C++/SystemC Synthesis

A comprehensive HLS flow taking C++ or SystemC as the design input and optimally targeting ASIC, eFPGA or FPGA implementations tuned for frequency and target technology.

Low-Power Solutions

When it comes to early design space exploration, power estimation, and optimizing for low-power ASIC RTL, Catapult generates highly efficient RTL that is optimized with our PowerPro technology under the hood.

Catapult High-Level Verification Solutions

Accelerate your High-Level Verification (HLV) flow with known and trusted methods using the Catapult HLV Platform. Reduce your overall SoC verification turnaround time and costs by up to 80% leveraging High-Level Design Checking, Code/Functional Coverage, and static plus formal methods.

Catapult Design Checker

Lint and formal analysis to validate your High-Level Synthesis source for correctness before synthesis or simulation. Avoid design problems and QoR issues that can occur when coding for HLS when using C++ or SystemC.

Catapult Coverage

Provides HLS-aware code coverage, including statement, branch, condition, FEC, and array access coverage. SystemVerilog inspired functional coverage with support for covergroups, coverpoints, bins, and crosses.

Catapult Formal Verification Tools

Formally find mistakes, ambiguities and problem design issues or user constraint mistakes early in the HLS process. Even with differences in timing, and interfaces, Catapult Formal enables verification and a coverage closure flow.