Catapult High-Level Synthesis & Verification Events

This webinar introduces a simple and robust quantization methodology based on value range analysis.

At the IP level, an ISP was created within a year using Catapult, a task that would have been impossible using traditional RTL. To reduce dependency on designer experience, we introduced an AI-assisted DSE tool. 

Find out more about the webinar "Architectural Improvements for Low-Power and Functional Safety of Dataflow CNN Accelerators Using HLS".

Tutorial will show how to verify a machine learning algorithm from Python code in a machine learning framework, like TensorFlow or Caffe, to RTL. The algorithm will be migrated from Python, to C++, and finally to RTL using HLS.

Learn how C++ and SystemC/MatchLib HLS is more than just converting SystemC to RTL. We’ll cover language choice, architecture exploration, power estimation and optimization that all work to deliver competitive RTL fast & cheap.

Design flow including HW/SW co-design and HLS that allows developers to migrate compute intensive functions from SW running on an embedded processor to a HW based accelerator as a loosely coupled bus-based peripheral.

Learn how you can use High-Level Synthesis to go from Python to synthesizable RTL to deploy a custom AI accelerator faster and easier than you thought possible. 

Tutorial will show how to verify a machine learning algorithm from Python code in a machine learning framework, like TensorFlow or Caffe, to RTL. The algorithm will be migrated from Python, to C++, and finally to RTL using HLS.

Cornell intros HiSparse: accelerator on sparse-matrix dense-vector multiplication. Using both HLS implementation and simulation, their sparse accelerators deliver promising speedup with increased bandwidth and energy efficiency.

FNAL demos that a NN autoencoder model can be implemented in a radiation-tolerant ASIC to perform lossy data compression. This alleviates the data transmission problem while preserving the detector energy profile's critical info.

5G standards open the world of hardware development to anyone that can build the best, cost-effective products. Catapult, Questa, and Veloce enable integrated, reliable design and verification solutions for 5G system design.

本ウェビナーでは、特別招待講演としてASA Microsystems社、社長、三輪 晴治氏をお迎えし、「日本半導体産業の寿命 ～ 新しい半導体製品をどんどん開発するために何がどうあるべきか ～」と題しまして、お届けいたします。

In this webinar, we will share this new model of data driven hardware design that produces dramatically better hardware and software – tightly optimized for specific applications.

This tutorial will demonstrate HLS algorithm transformation on an example algorithm from a full software implementation to a high performance, efficient implementation with a mix of hardware and software elements.

Overview of what HLS is and how it can be used to create application specific accelerators. It will show how these accelerators can be integrated into a processor-based system from a hardware and software perspective. 

HLS makes a true HW/SW co-design possible by enabling accurate partitioning
exploration and swapping of functionalities between SW and HW accelerator to
optimize bus traffic, memory utilization and processor load.

HLS Adoption for chip design is driven by increasing design & verification complexity and time to market pressures. HLS enables designers to get their chips to market faster by shortening the overall design & verification flow.

This talk will explore how HLS can be used to deliver the data needed to make critical design trade-off decisions and cover how HLS can enable system verification in an MBSE flow, and how HLS can mitigate supply chain risks.

To understand which Catapult HLS flow is better suited for our needs at JPL-NASA, we implemented Harris Corner Detector image processing core in both untimed C++ and timed SystemC. Lessons learned from each flow will be presented.

This tutorial will describe how HLS can be used to implement and verify accelerators for ML algorithms. It will cover how to explore architectural alternatives, and comparisons with more traditional acceleration approaches. 

This tutorial will approach the question of design quality from a unique perspective.

This workshop will show the example design running at different levels of abstraction, exploring the different verification objectives that can be achieve at each stage of the design process.

Harvard sheds light on their agile algorithm-hardware co-design and co-verification methodology powered by High-Level Synthesis, which enabled them to reduce front-end VLSI design efforts by orders of magnitude.

This session will show how to create different types of accelerators using HLS and how to integrate them into RISC-V processor designs. AI inferencing algorithm and an encryption algorithm will be used as examples.

Deploying an algorithm in hardware requires an understanding of the algorithm and its data dependencies. We’ll describe an automated way to gain these insights from a C++ description with an automated path to RTL though HLS.

Deploying an algorithm in hardware requires an understanding of the algorithm and its data dependencies. We’ll describe an automated way to gain these insights from a C++ description with an automated path to RTL though HLS.

This webinar demonstrates how one can achieve comprehensive verification faster at a higher level of abstraction but still apply known and trusted RTL verification techniques. 

The presentation will give a high-level technical overview of the Catapult HLS platform that you can use in your future projects to speed up your development process.

In this round table, we will discuss some interesting approaches of HW/SW codesign and the pros and cons of those approaches. Hosted by Anoop Saha and Russell Klein from Siemens and joined by Thierry Tambe from Harvard University.

This talk will focus on silicon for the edge, and the design choices that helps deployment of powerful machine learning algorithms on tiny low-cost energy-efficient hardware.

We will demonstrate how one can achieve comprehensive verification faster at a higher level of abstraction but still apply known and trusted RTL verification techniques.

AI is poised to become ubiquitous in embedded systems. Learn how inferencing can be effectively deployed in low power, computationally constrained devices without needing to bring along a really long extension cord.

Keynote covering enabling technologies – from HLS to hardware software codesign, covering the past, present and the future of silicon design process, the disruptions, and the latest technological trends.