The broadest portfolio of hardware design solutions for C++ and SystemC-based
High-Level Synthesis (HLS). Catapult's physically-aware, multi-VT mode, with
Low-Power estimation and optimization, plus a range of leading Verification
solutions make HLS from Siemens more than just "C to RTL".
The past several years have seen an explosion in the adoption of HLS for chip design driven by increasing design and verification complexity as well as time to market pressures. HLS enables designers to get their chips to market faster by shortening the overall design and verification flow.
Catapult Synthesis solutions from Siemens deliver C++ and SystemC language support, FPGA and ASIC independence, ASIC power estimation and optimization plus the latest in Physically aware multi-VT area and performance optimization.
Everything you need to accelerate your High-Level Verification flow. Reduce Verification time and costs by up to 80% leveraging Design Checking, Code and Functional Coverage plus Formal.
Take a look to find out how the Catapult High-Level Synthesis platform enables you to do more, and do it better. Learn about Deep Learning, Computer Vision, Communications, Video, and more with just a click. Siemens' High-Level Synthesis and Verification (HLS & HLV) tools deliver the competitive edge you need.