Catapult High-Level Synthesis and Verification

Catapult has the broadest portfolio of hardware design solutions for C++ and SystemC-based High-Level Synthesis (HLS). Catapult's physically-aware, multi-VT mode, with
Low-Power estimation and optimization, plus a range of leading Verification
solutions make Catapult HLS more than just "C to RTL".


Catapult Customers Discuss their Real-World use of HLS

The past several years have seen an explosion in the adoption of HLS for chip design driven by increasing design and verification complexity as well as time to market pressures. Catapult HLS enables designers to get their chips to market faster by shortening the overall design and verification flow.

Catapult High-Level Synthesis Solutions

Catapult High-Level Synthesis solutions deliver C++ and SystemC language support, FPGA and ASIC independence, ASIC power estimation and optimization plus the latest in Physically aware multi-VT area and performance optimization to elevate your designs.

Resource Library

Catapult High-Level Synthesis

Find out how the Catapult High-Level Synthesis and Verification platform enables you to do more, and do it better. Learn about AI/ML, Deep Learning, Computer Vision, Communications, Video, and more. Siemens' High-Level Synthesis and Verification (HLS & HLV) tools deliver the competitive edge you need.

Explore Catapult High-Level Synthesis' resources to learn more about its successful implementation across numerous applications and customers.