Overview
Catapult Formal Verification Tools
Formally find mistakes, ambiguities and undesirable design issues, user constraints problems early in the HLS design and verification process. Even with differences in language, timing, and interfaces, Catapult Formal Verification Tools enable verification and coverage closure flow at C-level.
Catapult Formal Verification Tools
HL centric apps are plug-in compatible with existing RTL flows & UVM principles, targeting:
- Check design for undefined behaviors
- Achieve coverage closure
- Detect setup mistakes that change design behavior
- Check implementation correctness
- Detect differences with bug hunting
Find Coverage Issues Before Synthesis Efficiently
• Waive unreachable coverage points for accurate coverage metrics
• Witness reachable coverage points for simulation replay, greater insight
• Plug-play integration with Catapult Coverage with industry standard UCDB database
Detect mistakes and setup constraints problems early
- Formally check memory setup
- Formally check for sufficient FIFO depth/size between blocks
Check implementation and detect differences early
- Detect Catapult inferred mistakes and constraints problems early
- Formally check sequential behavior maintain design behavior / intent
Find behavior differences early
Formally search for differences between the HLS model the HLS setup and created RTL. Significantly reduces the time and effort to establish confidence that the intended functionality is maintained without requiring exhaustive simulation. Mismatches are formally proven and flagged with counter-examples.
Ready to discuss Catapult Formal Verification Tools?
Any questions you may have, we will have the answers!
Email us at hls-hlv.sisw@siemens.com
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