Formally find mistakes, ambiguities and undesirable design issues, user constraints problems early in the HLS design and verification process. Even with differences in language, timing, and interfaces, Catapult Formal Verification Tools enable verification and coverage closure flow at C-level.
HL centric apps are plug-in compatible with existing RTL flows & UVM principles, targeting:
• Waive unreachable coverage points for accurate coverage metrics
• Witness reachable coverage points for simulation replay, greater insight
• Plug-play integration with Catapult Coverage with industry standard UCDB database
Formally search for differences between the HLS model the HLS setup and created RTL. Significantly reduces the time and effort to establish confidence that the intended functionality is maintained without requiring exhaustive simulation. Mismatches are formally proven and flagged with counter-examples.
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The Catapult High-Level Synthesis (HLS) On-Demand training library contains a set of learning paths with modules to introduce Engineers to HLS and High-Level Verification.
A group to discuss the finer points of Design and Verification using Siemens EDA's HLS & HLV tools. Join the discussion on new topics, features, content, and technical experts.
A free and open set of libraries implemented in standard C++ for bit-accurate hardware and software design. It's an open community for exchange of knowledge and IP for HLS that can be used to accelerate both research and design.
Blog covering next generation High-Level Synthesis (HLS) design and verification methodologies and techniques.
Access detailed documentation, releases, resources and more.
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