Providing class-leading products and methodology for High-Level design, Siemens delivers solutions at multiple points of the design process. Design Checking, Code and Functional Coverage and Formal verification for C++ and SystemC equivalence checking.
Accelerate your High-Level Verification (HLV) flow with known and trusted methods using the Catapult HLV Platform. Reduce your overall SoC verification turnaround time and costs by up to 80% leveraging High-Level Design Checking, Code/Functional Coverage, and static plus formal methods.
The past several years have seen an explosion in the adoption of HLS for chip design driven by increasing design and verification complexity as well as time to market pressures. Catapult HLS enables designers to get their chips to market faster by shortening the overall design and verification flow.