High-Level Verification Solutions

Providing class-leading products and methodology for High-Level design, Siemens delivers solutions at multiple points of the design process. Design Checking, Code and Functional Coverage and Formal verification for C++ and SystemC equivalence checking.

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Catapult High-Level Verification Solutions

Everything you need to accelerate your High-Level Verification flow. Reduce Verification time and costs by up to 80% leveraging Design Checking, Code and Functional Coverage plus Formal.

Catapult Design Checker

Lint and formal analysis to validate your HLS designs for correctness before synthesis. Avoid design problems and QoR issues that can occur when coding for HLS.

Catapult Coverage

Provides HLS-aware code coverage, including statement, branch, FEC, toggle and array access coverage. SV-inspired functional coverage with support for covergroups, coverpoints, bins and crosses.

Catapult Formal Verification Tools

Formally find mistakes, ambiguities and undesirable design issues, user constraints problems early in the HLS process. Even with differences in timing, and interfaces Catapult Formal enables verification and coverage closure flow.

SLEC System

Check the correctness of RTL against your High-Level models using SLEC. Enabling proof that specification and implementation are identical despite differences in language, timing, or abstraction.