Catapult Coverage

Catapult Coverage provides HLS-aware code coverage, including statement, branch, condition, FEC and array access coverage, for C++/SystemC HLS designs. It also provides SV-inspired functional coverage with support for covergroups, coverpoints, bins and crosses within C++/SystemC test benches.


An efficient approach to metrics driven HLV

Use traditional RTL metrics such as statement, branch, condition and expression coverage, combined with SystemVerilog-inspired functional coverage to achieve high quality HLS-aware coverage prior to High-Level Synthesis.

Coverage accelerates verification

C++/SystemC simulation executes 100’s of times faster than RTL simulation, enabling comprehensive verification of high-level system behavior. Catapult Coverage complements high level simulation with traditional RTL metrics such as statement, branch, condition and expression code coverage along with SystemVerilog-inspired functional coverage.

HLS-aware code coverage of C++/SystemC HLS designs

Catapult Coverage provides HLS-aware code coverage that, unlike software-centric coverage tools, recognizes how design constructs and HLS directives impact the resulting post-HLS hardware and thus takes these into consideration when collecting and reporting code coverage on HLS design source. Examples include function inlining and loop unrolling directives. Catapult Coverage also supports needed coverage types on HLS design source such as Condition and Focused Expression (FEC) coverage plus array access coverage.

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Functional Coverage inspired by SystemVerilog

Catapult Coverage provides for SV-inspired functional coverage with support for Covergroups, Coverpoints, Bins and Crosses within C++/SystemC test benches. A sample() method is also supported to specify when a covergroup should be sampled. As with traditional RTL, this functional coverage can be linked to test plan requirements.

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Data-Driven Verification Management with UCDB

Catapult Coverage writes coverage data to the Questa UCDB (Unified Coverage Database) for a complete set of post-processing Verification Management tools. UCDB enables data-driven verification management with support for analysis and reporting of coverage results, merging and ranking of tests, applying exclusions and integration of test plans.

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GUI based analysis

Integration with Questa Visualizer provides for GUI-based analysis of coverage data. This includes analyzing coverage results annotated on the HLS design source and hierarchy, a covergroup window to review functional coverage, the ability to readily perform desired ranking and easy mouse-button click specification of desired coverage exclusions.

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Catapult on-demand training

The Catapult High-Level Synthesis (HLS) on-demand training library contains a set of learning paths with modules to introduce engineers to HLS and high-level verification.

High-Level Synthesis and Verification Group

A group to discuss the finer points of design and verification using Siemens EDA HLS and HLV tools. Join the discussion on new topics, features, content and technical experts.


A free and open set of libraries implemented in standard C++ for bit-accurate hardware and software design. It's an open community for exchange of knowledge and IP for HLS that can be used to accelerate both research and design.

HLS Design and Verification Blog

Blog covering next generation high-level synthesis (HLS) design and verification methodologies and techniques.


Catapult Support

Access detailed documentation, releases, resources and more.

EDA consulting

Helping you achieve maximum business impact by addressing complex technology and enterprise challenges with a unique blend of development and design experience and methodology expertise.