{"showBreadcrumbs":true,"breadcrumbs":[{"title":"Siemens EDA Software","path":"/en-US/"},{"title":"IC Tool Portfolio","path":"/en-US/ic"},{"title":"Catapult High-Level Synthesis","path":"/en-US/ic/catapult-high-level-synthesis"},{"title":"High-Level Verification","path":"/en-US/ic/catapult-high-level-synthesis/hls-verification"},{"title":"Catapult Coverage","path":""}],"tagline":"Overview","title":"Catapult Coverage","description":"Catapult Coverage provides HLS-aware code coverage, including statement, branch, FEC, toggle and array access coverage, for C++/SystemC HLS designs. It also provides SV-inspired functional coverage with support for covergroups, coverpoints, bins and crosses within C++/SystemC test benches.","pricingCurrency":"US$","image":{"url":"//images.ctfassets.net/17si5cpawjzf/1sPIuqmJfwOBw8GR4ytR5K/40b5e8cd322148733c474f1975129666/fc-catapult-coverage-1120-1-promo-640x480.jpg?w=640","alt":"Coverage provides HLS-aware code coverage for C++/SystemC HLS designs.","linkData":"{\"name\":\"fc-catapult-coverage-1120-1-promo-640x480\",\"id\":\"1sPIuqmJfwOBw8GR4ytR5K\",\"contentType\":\"image/jpeg\"}"},"secondaryButton":{"text":"Read Fact Sheet","resource":{"ids":["117nas4GgrkL7g0WNcgyYw"],"mode":"selected","query":{"q":"Catapult High-Level Synthesis and Verification","sorts":[{"field":"publishedDate","order":"desc"}],"filters":[{"field":"collection","values":["resource"],"operator":"OR"}],"postFilters":[],"verboseLocalization":true},"idsQuery":{"size":1,"filters":[{"field":"collection","values":["resource"],"operator":"OR"},{"field":"id","values":["117nas4GgrkL7g0WNcgyYw"],"operator":"OR"}],"verboseLocalization":true}},"env":"master"}}
Overview

Catapult Coverage

Catapult Coverage provides HLS-aware code coverage, including statement, branch, FEC, toggle and array access coverage, for C++/SystemC HLS designs. It also provides SV-inspired functional coverage with support for covergroups, coverpoints, bins and crosses within C++/SystemC test benches.

Coverage provides HLS-aware code coverage for  C++/SystemC HLS designs.

Catapult Coverage Resources

Key Features

Catapult Coverage Accelerates Verification Before RTL

Use traditional RTL metrics such as statement, branch, expression, and toggle coverage, combined with functional verification techniques from SystemVerilog to reach high quality HLS-aware coverage without slow and expensive RTL Simulation.

HLS-aware Code Coverage of C++/SystemC HLS Designs

Catapult Coverage uses the Questa UCDB (Unified Coverage Database) thus providing users with a rich set of Verification Management tools. This includes the means to view, analyze and manage the coverage data, merge and rank coverage results from multiple tests, apply exclusions, generate desired reports and integrate test plans.

Key Features of HLS Aware Coverage

Functional Coverage Inspired by SystemVerilog

Catapult Coverage provides for SV-inspired functional coverage with support for Covergroups, Coverpoints, Bins, and Crosses within C++/SystemC test benches. A sample() method is also supported to specify when a cover group should be sampled. As with traditional RTL, this functional coverage can be linked to test plan requirements.

Image of inspired Functional Coverage

UCDB for Verification Management

Catapult Coverage writes coverage data to the Questa UCDB (Unified Coverage Database) that provides the user with a complete set of post-processing Verification Management tools. This includes support for analysis and reporting of coverage results, merging and ranking of tests, applying exclusions and integration of test plans.

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