C++/SystemC/RTL Formal
Formally verify the correctness of hand-written RTL vs High-Level models using Sequential Logic Equivalence Checking. Even with differences in language, timing, and interfaces, SLEC-System verifies manual RTL with Catapult Formal proving C++ vs Catapult generated RTL.
Formal Verification of C++/SystemC/RTL
When designers move high-level design descriptions into RTL, or make power optimizations to RTL, they need to know if the result is functionally equivalent to the original, possibly high-level description. SLEC delivers solutions for manual, HLS, and power optimization RTL verification.
SLEC SOLUTIONS
Leading Formal Equivalency Checking
Paired with a range of best-in-class engines, this powerful verification approach enables bug hunting, bounded-check, and full-proof strategies. SLEC is designed to complement typical simulation-based verification, and it is integrated with debug tools like Siemens EDA Visualizer for understanding falsifications.
SLEC-SYSTEM
Manual Formal Equivalence Checking
For the toughest manual formal verification challenges involving complex implementations in hand-coded RTL. SLEC-System delivers capabilities enabling formal proof of design blocks as challenging as double precision floating point multiplication, mult-add and other problems that simply cannot be exhaustively simulated in RTL.
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