Formally verify the correctness of hand-written or Catapult-generated RTL vs High-Level models using Sequential Logic Equivalence Checking. Even with differences in language, timing, and interfaces, SLEC-System verifies manual RTL with SLEC-HLS proving C++ vs Catapult generated RTL.
When designers move high-level design descriptions into RTL, or make power optimizations to RTL, they need to know if the result is functionally equivalent to the original, possibly high-level description. SLEC delivers solutions for manual, HLS, and power optimization RTL verification.
Paired with a range of best-in-class engines, this powerful verification approach enables bug hunting, bounded-check, and full-proof strategies. SLEC is designed to complement typical simulation-based verification, and it is integrated with debug tools like Siemens EDA Visualizer for understanding falsifications.
For the toughest manual formal verification challenges involving complex implementations in hand-coded RTL. SLEC-System delivers capabilities enabling formal proof of design blocks as challenging as double precision floating point multiplication, mult-add and other problems that simply cannot be exhaustively simulated in RTL.
An external testbench or SCVerify RTL simulation can provide good functional verification confidence. SLEC-HLS enhances confidence by verifying that Catapult high-level synthesis RTL has exact functional equivalency to the source C++ without requiring exhaustive simulation. Mismatches are formally proven and flagged with counter-examples.
When making optimizations automatically for Power, PowerPro Optimizer users now benefit from an automated setup for SLEC that proves the sequential equivalence between the original and optimized RTL. SLEC-Pro can also be leveraged in conjunction with RTL optimized as part of the Catapult HLS Low Power flow.
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