Catapult accelerates exploring different architecture tradeoffs and measures the power, performance and area for each HLS solution. Catapult automatically performs fine grained power-saving optimizations aimed at minimizing switching activity in the RTL to deliver the greatest power savings.
Using the HLS testbench configuration already used for Verification, Catapult automatically drives simulation of generated RTL solutions. Captured switching data and technology library enable the embedded PowerPro engine to give designers rapid feedback on the approximate power cost of HLS blocks, enabling exploration and architectural optimization.
With the deep sequential analysis capability of PowerPro, Catapult first-pass optimizations are refined for power reduction across the entire design. Enhancements to the RTL are based on observability and stability analysis using testbench switching activity to guide the value of the optimization. Formal verification of RTL to optimized RTL is available.
The Catapult High-Level Synthesis (HLS) On-Demand training library contains a set of learning paths with modules to introduce Engineers to HLS and High-Level Verification.
A group to discuss the finer points of Design and Verification using Siemens EDA's HLS & HLV tools. Join the discussion on new topics, features, content, and technical experts.
A free and open set of libraries implemented in standard C++ for bit-accurate hardware and software design. It's an open community for exchange of knowledge and IP for HLS that can be used to accelerate both research and design.
Blog covering next generation High-Level Synthesis (HLS) design and verification methodologies and techniques.
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