C++/SystemC Synthesis
Catapult is the leading HLS solution for ASIC and FPGA. Supporting C++ and SystemC, designers work in their preferred language, moving up in productivity and quality. With 80% less coding, and simulation speeds up to 1,000x faster than Verilog. HLS Design and verification is the edge you need.
C++/SystemC Synthesis Resources
Blazing Fast Design, Verification & Implementation
HLS is more than just turning C++/SystemC into RTL. Catapult delivers ASIC & FPGA “right first time” RTL for design, verification and implementation. Avoid surprises with Design Checking, improve functional coverage with Catapult Coverage, and close timing on the latest nodes with Catapult Physical.
LANGUAGE FREEDOM
Native Dual-Language Support of SystemC and C++
C++ or SystemC is a choice that gives teams the flexibility to decide what is the most effective methodology for their design task. Whether it be the superior simulation and verification speed of sequential C++ with the AC data types (hlslibs.org), or explicit concurrency modeling with SystemC and MatchLib (using the AC types), Catapult has you covered.
ADVANCED DESIGN CHECKING
Catapult Design Checker Finds Bugs Before Synthesis
Find coding bugs before you even knew you had them! Without a testbench and by using a blend of lint and formal engine analysis, Catapult identifies bad logic-creating uninitialized variables, array bounds violations, and other coding problems that can appear in C++ or SystemC. Catapult even provides feedback on potential HLS QoR problems before synthesis.
COVERAGE DRIVEN VERIFICATION
Catapult Coverage Accelerates Verification Before RTL
Use traditional RTL metrics such as statement, branch, expression, and toggle coverage. Combine with functional verification techniques from SystemVerilog to reach high quality HLS-aware coverage without slow and expensive RTL Simulation. Faster C++/SystemC simulation speeds boost your verification efforts and “right first time” RTL delivery.
"With the Catapult Flow, RTL debug literally disappears. The C model is validated in its environment, and from there correct-by-construction RTL is created. This reduces the verification effort dramatically."
Giuseppe Bonanno, Senior Engineer R&D, STMicroelectronics
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