C++/SystemC Synthesis
Catapult is the leading HLS solution for ASIC and FPGA. Supporting C++ and SystemC, designers work in their preferred language, moving up in productivity and quality. With 80% less coding, and simulation speeds up to 1,000x faster than Verilog. HLS Design and verification is the edge you need.
Catapult C++/SystemC Synthesis Resources
Blazing Fast Design, Verification & Implementation
HLS is more than just C++/SystemC to RTL. Catapult delivers ASIC & FPGA “right first time” RTL for design, verification and implementation. Avoid surprises with Design Checking, improve coverage with Catapult Coverage, and close timing on the latest nodes with a multi-VT Physically aware flow.
Native Dual-Language Support of SystemC and C++
C++ or SystemC is a choice that gives teams the flexibility to decide what is the most effective methodology for their design task. Whether it be the superior simulation and verification speed of sequential C++ with the AC data types (hlslibs.org), or explicit concurrency modeling with SystemC and MatchLib (using the AC types), Catapult has you covered.
Catapult Design Checker Finds Bugs Before Synthesis
Find coding bugs before you even knew you had them! Without a testbench and by using a blend of lint and formal engine analysis, Catapult identifies bad logic-creating uninitialized variables, array bounds violations, and other coding problems that can appear in C++ or SystemC. Catapult even provides feedback on potential HLS QoR problems before synthesis.
Catapult Coverage Accelerates Verification Before RTL
Use traditional RTL metrics such as statement, branch, expression, and toggle coverage. Combine with functional verification techniques from SystemVerilog to reach high quality HLS-aware coverage without slow and expensive RTL Simulation. Faster C++/SystemC simulation speeds boost your verification efforts and “right first time” RTL delivery.
With the Catapult Flow, RTL debug literally disappears. The C model is validated in its environment, and from there correct-by-construction RTL is created. This reduces the verification effort dramatically.
HLS Design & Verification Blog
Blog covering next generation High-Level Synthesis (HLS) design and verification methodologies and techniques.
Catapult On-Demand Training
The Catapult High-Level Synthesis (HLS) On-Demand training library contains a set of learning paths with modules to introduce Engineers to HLS and High-Level Verification.
Join the High-Level Synthesis & Verification Group
A group to discuss the finer points of Design and Verification using Siemens EDA's HLS & HLV tools. Join the discussion on new topics, features, content, and technical experts.
EDA consulting
Helping you achieve maximum business impact by addressing your complex technology and enterprise challenges with a unique blend of development experience, design knowledge, and methodology expertise.