HLS is more than just C++/SystemC to RTL. Catapult delivers ASIC & FPGA “right first time” RTL for design, verification and implementation. Avoid surprises with Design Checking, improve coverage with Catapult Coverage, and close timing on the latest nodes with a multi-VT Physically aware flow.
C++ or SystemC is a choice that gives teams the flexibility to decide what is the most effective methodology for their design task. Whether it be the superior simulation and verification speed of sequential C++ with the AC data types (hlslibs.org), or explicit concurrency modeling with SystemC and MatchLib (using the AC types), Catapult has you covered.
Find coding bugs before you even knew you had them! Without a testbench and by using a blend of lint and formal engine analysis, Catapult identifies bad logic-creating uninitialized variables, array bounds violations, and other coding problems that can appear in C++ or SystemC. Catapult even provides feedback on potential HLS QoR problems before synthesis.
Use traditional RTL metrics such as statement, branch, expression, and toggle coverage. Combine with functional verification techniques from SystemVerilog to reach high quality HLS-aware coverage without slow and expensive RTL Simulation. Faster C++/SystemC simulation speeds boost your verification efforts and “right first time” RTL delivery.
Blog covering next generation High-Level Synthesis (HLS) design and verification methodologies and techniques.
The Catapult High-Level Synthesis (HLS) On-Demand training library contains a set of learning paths with modules to introduce Engineers to HLS and High-Level Verification.
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