C++/SystemC Synthesis

Catapult is the leading HLS solution for ASIC and FPGA. Supporting C++ and SystemC, designers work in their preferred language, moving up in productivity and quality. With 80% less coding, and simulation speeds up to 1,000x faster than Verilog. HLS Design and Verification is the edge you need.


Superior Design, Verification, and Implementation

Catapult makes quality RTL for ASIC/FPGA from C++/SystemC in half the time of hand-coding. Design Space Exploration, downstream RTL synthesis integration, plus power estimation/optimization enables better designs. Design Checking, Code Coverage, and Formal, reduce RTL verification cost by up to 80%.

Language Freedom

Native Dual-Language Support of SystemC and C++

C++ or SystemC is a choice that gives teams the flexibility to decide what is the most effective methodology for their design task. Whether it be the superior simulation and verification speed of sequential C++ with the AC data types (hlslibs.org), or explicit concurrency modeling with SystemC and MatchLib (using the AC types), Catapult has you covered.

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Advanced Design Checking

Catapult Design Checker Finds Bugs Before Synthesis

Find coding bugs before you even knew you had them! Without a testbench and by using a blend of lint and formal engine analysis, Catapult identifies bad logic-creating uninitialized variables, array bounds violations, and other coding problems that can appear in C++ or SystemC. Catapult even provides feedback on potential HLS QoR problems before synthesis.

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Coverage and Verification

Catapult Coverage Accelerates Verification Before RTL

Use traditional RTL metrics such as statement, branch, expression, and toggle coverage. Combine with functional verification techniques from SystemVerilog to reach high quality HLS-aware coverage without slow and expensive RTL Simulation. Faster C++/SystemC simulation speeds boost your verification efforts and “right first time” RTL delivery.

Catapult Coverage Driven Verification
With the Catapult Flow, RTL debug literally disappears. The C model is validated in its environment, and from there correct-by-construction RTL is created. This reduces the verification effort dramatically.
Giuseppe Bonanno, Senior Engineer R&D, STMicroelectronics

Catapult On-Demand Training

The Catapult High-Level Synthesis (HLS) On-Demand training library contains a set of learning paths with modules to introduce Engineers to HLS and High-Level Verification.

Join the High-Level Synthesis & Verification Group

A group to discuss the finer points of Design and Verification using Siemens EDA's HLS & HLV tools. Join the discussion on new topics, features, content, and technical experts.


A free and open set of libraries implemented in standard C++ for bit-accurate hardware and software design. It's an open community for exchange of knowledge and IP for HLS that can be used to accelerate both research and design.

HLS Design & Verification Blog

Blog covering next generation High-Level Synthesis (HLS) design and verification methodologies and techniques.


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Helping you achieve maximum business impact by addressing complex technology and enterprise challenges with a unique blend of development and design experience and methodology expertise.