With leading C++ and SystemC support, Catapult offers advanced HLS tools for FPGA, eFPGA, and ASIC. Catapult will accelerate your success with solutions for outstanding Quality of Results through physical awareness, low-power estimation-optimization, design checking, lint, formal, and code coverage.
HLS, C-level design, and verification are reducing entire project development times by half or more in ASIC and FPGA designs today. This seminar uses an AXI-based AI/ML accelerator to demonstrate how HLS can rapidly go from an algorithm, through C-based design, system-level performance analysis, and comprehensive verification with RTL coverage closure. Watch it now, get the code examples, and resources.
Catapult Synthesis solutions from Siemens deliver C++ and SystemC language support, FPGA and ASIC independence, ASIC power estimation and optimization plus the latest in Physically aware multi-VT area and performance optimization.
Take a look to find out how the Catapult High-Level Synthesis platform enables you to do more, and do it better. Learn about Deep Learning, Computer Vision, Communications, Video, and more with just a click. Siemens' High-Level Synthesis and Verification (HLS & HLV) tools deliver the competitive edge you need.