With leading C++ and SystemC support, Catapult offers advanced HLS tools for FPGA, eFPGA, and ASIC. Catapult will accelerate your success with solutions for outstanding Quality of Results through physical awareness, low-power estimation-optimization, design checking, lint, formal, and code coverage.
The past several years have seen an explosion in the adoption of HLS for chip design driven by increasing design and verification complexity as well as time to market pressures. HLS enables designers to get their chips to market faster by shortening the overall design and verification flow.
Catapult Synthesis solutions from Siemens deliver C++ and SystemC language support, FPGA and ASIC independence, ASIC power estimation and optimization plus the latest in Physically aware multi-VT area and performance optimization.
Take a look to find out how the Catapult High-Level Synthesis platform enables you to do more, and do it better. Learn about Deep Learning, Computer Vision, Communications, Video, and more with just a click. Siemens' High-Level Synthesis and Verification (HLS & HLV) tools deliver the competitive edge you need.