Overview
Catapult Design Checker
Catapult brings lint and formal analysis to validate your C++/SystemC designs for correctness before synthesis. Avoid design problems associated with uninitialized memory reads, out of bound array accesses, incomplete switch statements and QoR issues that can occur when coding for HLS.
Verification at the C++ cuts costs by up to 80%
Formal & Static Lint for C++/SystemC
Catapult Design Checker provides multiple checking modes that remove the need for simulation-based debug of problems in your design. Coding issues, QoR problems, and potential C++/SystemC to RTL mismatches and ambiguities, are caught rapidly giving exact feedback as to the source and cause.
Static Lint for QoR
Finding common problems in coding before Synthesis is easy with Catapult Design Checker.
Focus On Specific Problems
Catapult Design Checker enables the user to customize and prioritize checks to focus on pressing problems while reducing noise from already known issues.
Catapult On-Demand Training
The Catapult High-Level Synthesis (HLS) On-Demand training library contains a set of learning paths with modules to introduce Engineers to HLS and High-Level Verification.
Join the High-Level Synthesis & Verification Group
A group to discuss the finer points of Design and Verification using Siemens EDA's HLS & HLV tools. Join the discussion on new topics, features, content, and technical experts.
HLSLibs
A free and open set of libraries implemented in standard C++ for bit-accurate hardware and software design. It's an open community for exchange of knowledge and IP for HLS that can be used to accelerate both research and design.
HLS Design & Verification Blog
Blog covering next generation High-Level Synthesis (HLS) design and verification methodologies and techniques.
EDA consulting
Helping you achieve maximum business impact by addressing complex technology and enterprise challenges with a unique blend of development and design experience and methodology expertise.