Automatic Push-Button Solutions

Questa Formal Verification Apps

Questa Formal Verification Apps find obscure bugs, increasing design confidence through exhaustive analysis, before simulation test environments are available. Questa Formal apps boost productivity and functional verification quality by targeting verification tasks that are difficult to complete.

Formal Trends & Technologies

Questa Formal Verification Apps

Questa Formal Verification Apps complement simulation-based RTL design verification by analyzing all possible design behaviors to detect any reachable error states. This analysis ensures critical control blocks work correctly in all cases and locates design errors that may be missed in simulation.

STATIC RTL BUG HUNTING

Questa AutoCheck

A fully-automatic formal bug hunting app that finds deeply hidden bugs due to common RTL coding errors, AutoCheck makes it possible to eliminate a wide range of bugs without a testbench.

STATIC & DYNAMIC CONNECTIVITY

Questa Connectivity Check

The Questa Connectivity Check app is a fully automated solution for exhaustively verifying static and dynamic connectivity without requiring knowledge of formal or property specification languages.

CODE COVERAGE CLOSURE

Questa Covercheck

Questa CoverCheck is an automatic formal solution for achieving code coverage closure faster, that addresses an incontrovertible fact of verification: some fraction of uncovered code always remains.

ASSERTION-BASED VERIFICATION

Questa Formal Assertion Library

A Formal Assertion Library improves quality and reduces schedules by building protocol and methodology expertise into packages of reusable assertions that support popular industry-standard interfaces.

ROOT CAUSE POST-SILICON BUGS

Questa Post-Silicon Debug

The Questa Post Silicon Debug app leverages formal analysis and property synthesis to rapidly root cause bugs in logic deep within an SoC and prove fixes will not break anything else.

EXHAUSTIVE VERIFICATION

Questa Property Checking

PropCheck exhaustively discovers any design errors that can occur, without needing specific stimulus to detect the bug. This ensures that the verified design is bug-free in all legal input scenarios.

REGISTER VERIFICATION

Questa Register Check

Questa Register Check app automates exhaustive verification of control&status register behavior against CSV or IP-XACT register specification.

SECURE HW PATHS ANALYSIS

Questa Secure Check

The Questa Secure Check app is a fully automated solution for exhaustively verifying that only the paths you specify can reach security or safety-critical storage elements.

RTL CODE BLOCK COMPARISONS

Questa SLEC

Questa SLEC automatically compares specification RTL and implementation RTL code blocks using exhaustive formal analysis. No knowledge of formal or property specification languages is required.

X-STATE VERIFICATION

Questa X-Check

Questa X-Check is an automated application that exhaustively roots out ‘X’ issues without a testbench.

Live & On-Demand

Featured Formal Verification Webinars

Which is better – linting tools or formal auto checking tools? Backers of either hold ardent opinions of their relative merits, and like a proverbial cage match, would love to see their champion emerge as the winner in a contest of verification tools.

But we have different view – Lint and Formal AutoChecking tools can be used together to increase the quality of RTL deliverables. In this session we’ll start with the similarities and differences between Lint and Formal AutoChecking tools. We’ll describe checks run by Lint and Formal AutoChecking Tools, where they are distinct, and where there is overlap. We’ll recommend when to use Lint, when to use AutoCheck, and when to use both. This session will be highly interactive, after an overview of the tools we will review code examples and vote on which tool would be used to find the violations in the code.

Wednesday, June 15th

Lint vs Formal AutoCheck

LIVE WEBINAR

In this session you will gain an understanding of the similarities and differences between Lint and Formal AutoChecking tools, and how they can be used together to increase the quality of RTL deliverables.

Modern formal tools like Questa PropCheck automate the abstraction of many DUT elements; saving you setup time up-front, as well as wall clock run time and memory usage. But there are some circuit elements that the tools just can’t infer on their own from the raw RTL. This is where you come in, using the contents of this webinar to guide you.

Formal Analysis Performance

Fast, Scalable Formal Verification Made Easy

ON-DEMAND WEBINAR

In this webinar we'll be discussing the following techniques: Basic abstraction, setting up & optimizing constraints, Data Independence & Non-Determinism. These methods are easy-to-apply, increasing formal analysis performance.

This webinar will introduce you to a verification flow for designers that can help prevent early project issues, which when used result in lower cost, repeatable project attainment – without the silly excuses.

RTL Quality

‘The Dog Ate my RTL’ Doesn’t Work Anymore

ON-DEMAND WEBINAR

In this webinar, you will learn how non-optimal RTL quality affects your development, why providing the highest quality RTL improves overall team performance and how to accomplish an improved RTL quality-focused flow.

Verifying changes to RTL and testbench code prior to releasing to the rest of your team is the best way to avoid committing bugs that cause massive, team-wide disruptions. This webinar takes you through example tool flows that, when used within a Continuous Integration (CI) system, can avoid or even eliminate those bugs and disruptions.

RTL & Testbench

Practical Flows for Continuous Integration

ON-DEMAND WEBINAR

In this webinar we’ll teach you how to use a collection of tools – both formal and simulation – as part of a comprehensive approach to verifying RTL and testbench changes before
releasing them to your team.

In this webinar, we will show how with a little design knowledge and forethought on your part, you can leverage these two principals to cut down your formal analysis to a matter of minutes vs. hours.

FORMAL 101

Data Independence and Non-Determinism Made Easy

ON-DEMAND WEBINAR

In this webinar, we will show how with a little design knowledge and forethought on your part, you can leverage these two principals (DI and ND) to cut down your formal analysis to a matter of minutes vs. hours.

In this webinar, we will show you how to use IEEE standard property checking code (SVA) and off-the-shelf formal tools to quickly and exhaustively verify data transport through the DUT matches the specification.

FORMAL 101

Scoreboarding and Data Integrity Verification Made Easy

ON-DEMAND WEBINAR

In this webinar, we will show you how to use IEEE standard property checking code (SVA) and off-the-shelf formal tools to quickly and exhaustively verify data transport through the DUT matches the specification.

In this webinar we will show you how to write optimal constraints for formal analysis; and how to deliberately under- and over-constrain the analysis to learn more about the effectiveness of the constraints.

FORMAL 101

Setting Up & Optimizing Constraints

ON-DEMAND WEBINAR

In this webinar we will show you how to write optimal constraints for formal analysis; and how to deliberately under- and over-constrain the analysis to learn more about the effectiveness of the constraints.

Formal verification algorithms can struggle to read-in and analyze DUTs with very large state spaces. Specifically, circuit elements like counters and memories can introduce a lot of state bits and sequential state depth that can bring a formal analysis to a grinding halt. The solution is to “abstract away” such parts of the DUT by either swapping in simplified models of these elements, or by safely removing them completely (electronically, without touching your golden RTL source code).

FORMAL 101

Basic Abstraction Techniques

ON-DEMAND WEBINAR

In this webinar you will learn the types of DUT constructs that commonly cause formal analysis trouble, and how to apply time-tested techniques to safely abstract them away so that formal verification can rapidly reach closure.

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Verification Academy provides the skills necessary to mature an organization's functional verification process capabilities, providing a methodological bridge between high-level value propositions and the low-level details.

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Verification Horizons Blog

Insight and updates on concepts, values, standards, methodologies, and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

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Verification Horizons Issue

The Verification Horizons publication provides concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

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