The automated Questa X-Check app is designed to automatically employ formal analysis to exhaustively identify ‘X’ propagation issues in your design. Specifically, taking your RTL and a spec of your initialization sequence as input Questa X-Check begins.
An undefined signal at a critical control junction in a design, or a register unexpectedly loaded with garbage, can quickly cascade into a perplexing, show-stopping bug. Unfortunately, the handling ‘X’ level signals differ in logic synthesis and simulation. In the former case, ‘X’ is treated as a “don’t care”; the latter ‘X’ is treated as an “unknown”.
Circuit start-up & initialization
Low power-related optimizations
Gate level verification
Verification Academy provides the skills necessary to mature an organization's functional verification process capabilities, providing a methodological bridge between high-level value propositions and the low-level details.
Insight and updates on concepts, values, standards, methodologies, and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.
The Verification Horizons publication provides concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.