The immediate challenge is “observability” when you suspect a certain cluster or IP is the culprit. The ability to setup particular initial test conditions, probes, and constrained-random stimuli to reach the internal areas of the DUT is a real challenge given the SoC is in its fully realized state.
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Once assertions describing the desired behaviors are synthesized into the DUT on-board the hardware-assisted verification platform, the Questa Post-Silicon Debug app leverages the formal-based Questa Property Checking app (PropCheck) to bug hunt for the root cause of the observed failure.
Leverage formal analysis
The Questa Post-Silicon Debug app leverages formal analysis, as well as property synthesis, to rapidly give you the observability you need to root cause bugs in logic deep within the SoC, and prove fixes don’t break anything else.
Complex SoCs are challenging
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Verification Academy provides the skills necessary to mature an organization's functional verification process capabilities, providing a methodological bridge between high-level value propositions and the low-level details.
Insight and updates on concepts, values, standards, methodologies, and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.
The Verification Horizons publication provides concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.