Questa Post-Silicon Debug

Overview
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Overview

Questa Post-Silicon Debug

The immediate challenge is “observability” when you suspect a certain cluster or IP is the culprit. The ability to setup particular initial test conditions, probes, and constrained-random stimuli to reach the internal areas of the DUT is a real challenge given the SoC is in its fully realized state.

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Updated 4.22.21
Key Features

Formally explore all input stimuli and transactions

Once assertions describing the desired behaviors are synthesized into the DUT on-board the hardware-assisted verification platform, the Questa Post-Silicon Debug app leverages the formal-based Questa Property Checking app (PropCheck) to bug hunt for the root cause of the observed failure.

Leverage Formal Analysis

Rapidly Root Cause Post-Silicon Bugs and Validate Fixes

The Questa Post-Silicon Debug app leverages formal analysis, as well as property synthesis, to rapidly give you the observability you need to root cause bugs in logic deep within the SoC, and prove fixes don’t break anything else.

Questa Formal Verification - Post Silicon Debug - Validates Fixes are Exhaustive
Live & On-Demand

Featured Formal Verification Webinars

Verifying changes to RTL and testbench code prior to releasing to the rest of your team is the best way to avoid committing bugs that cause massive, team-wide disruptions. This webinar takes you through example tool flows that, when used within a Continuous Integration (CI) system, can avoid or even eliminate those bugs and disruptions.
ON-DEMAND WEBINAR
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Practical Flows for Continuous Integration

In this webinar we’ll teach you how to use a collection of tools – both formal and simulation – as part of a comprehensive approach to verifying RTL and testbench changes before
releasing them to your team.

In this webinar, we will show how with a little design knowledge and forethought on your part, you can leverage these two principals to cut down your formal analysis to a matter of minutes vs. hours.
FORMAL 101
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Data Independence and Non-Determinism Made Easy

ON-DEMAND WEBINAR

In this webinar, we will show how with a little design knowledge and forethought on your part, you can leverage these two principals (DI and ND) to cut down your formal analysis to a matter of minutes vs. hours.

In this webinar, we will show you how to use IEEE standard property checking code (SVA) and off-the-shelf formal tools to quickly and exhaustively verify data transport through the DUT matches the specification.
FORMAL 101
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Scoreboarding and Data Integrity Verification Made Easy

ON-DEMAND WEBINAR

In this webinar, we will show you how to use IEEE standard property checking code (SVA) and off-the-shelf formal tools to quickly and exhaustively verify data transport through the DUT matches the specification.

In this webinar we will show you how to write optimal constraints for formal analysis; and how to deliberately under- and over-constrain the analysis to learn more about the effectiveness of the constraints.
FORMAL 101
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Setting Up & Optimizing Constraints

ON-DEMAND WEBINAR

In this webinar we will show you how to write optimal constraints for formal analysis; and how to deliberately under- and over-constrain the analysis to learn more about the effectiveness of the constraints.

Formal verification algorithms can struggle to read-in and analyze DUTs with very large state spaces. Specifically, circuit elements like counters and memories can introduce a lot of state bits and sequential state depth that can bring a formal analysis to a grinding halt. The solution is to “abstract away” such parts of the DUT by either swapping in simplified models of these elements, or by safely removing them completely (electronically, without touching your golden RTL source code).
FORMAL 101
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Basic Abstraction Techniques

ON-DEMAND WEBINAR

In this webinar you will learn the types of DUT constructs that commonly cause formal analysis trouble, and how to apply time-tested techniques to safely abstract them away so that formal verification can rapidly reach closure.

FORMAL TRENDS & TECHNOLOGIES

Questa Formal Verification Resources

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Verification Academy

Verification Academy provides the skills necessary to mature an organization's functional verification process capabilities, providing a methodological bridge between high-level value propositions and the low-level details.

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Verification Horizons Blog

Insight and updates on concepts, values, standards, methodologies, and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

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Verification Horizons Issue

The Verification Horizons publication provides concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

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