{"showBreadcrumbs":true,"breadcrumbs":[{"title":"Siemens EDA Software","path":"/en-US/"},{"title":"IC Tool Portfolio","path":"/en-US/ic"},{"title":"Advanced Verification","path":"/en-US/ic/questa"},{"title":"Questa Formal","path":"/en-US/ic/questa/formal-verification"},{"title":"Questa Post-Silicon Debug","path":""}],"tagline":"Overview","title":"Questa Post-Silicon Debug","description":"The immediate challenge is “observability” when you suspect a certain cluster or IP is the culprit. The ability to setup particular initial test conditions, probes, and constrained-random stimuli to reach the internal areas of the DUT is a real challenge given the SoC is in its fully realized state.","pricingCurrency":"US$","image":{"url":"//images.ctfassets.net/17si5cpawjzf/450VmTjTmuB189tWcBAEQL/044e8e9f1ee9933d0835c0b5cc1dea24/dvt-questa-formal-verification-as195008932-promo-640x480.jpg?w=640","alt":"Stylized IC with components rising to create a \"cityscape\" | The Questa Post Silicon Debug app validates that RTL fixes effectively and completely addresses failures","linkData":"{\"name\":\"dvt-questa-post-silicon-debug-as195008932-640x480\",\"id\":\"450VmTjTmuB189tWcBAEQL\",\"contentType\":\"image/jpeg\"}"},"secondaryButton":{"text":"Read Fact Sheet","resource":{"ids":["3a9SzbqEqtuSsfmisoDCtW"],"mode":"selected","query":{"q":"Questa Formal Applications Datasheet","sorts":[{"field":"publishedDate","order":"desc"}],"filters":[{"field":"collection","values":["resource"],"operator":"OR"}],"postFilters":[],"verboseLocalization":true},"idsQuery":{"size":1,"filters":[{"field":"collection","values":["resource"],"operator":"OR"},{"field":"id","values":["3a9SzbqEqtuSsfmisoDCtW"],"operator":"OR"}],"verboseLocalization":true}},"env":"master"},"phoneIcon":true,"moreInformation":"Get in touch with our sales team 1-800-547-3000 "}
The immediate challenge is “observability” when you suspect a certain cluster or IP is the culprit. The ability to setup particular initial test conditions, probes, and constrained-random stimuli to reach the internal areas of the DUT is a real challenge given the SoC is in its fully realized state.
Get in touch with our sales team 1-800-547-3000
Questa Post-Silicon Debug Resources
Key Features
Formally explore all input stimuli and transactions
Once assertions describing the desired behaviors are synthesized into the DUT on-board the hardware-assisted verification platform, the Questa Post-Silicon Debug app leverages the formal-based Questa Property Checking app (PropCheck) to bug hunt for the root cause of the observed failure.
Leverage Formal Analysis
Rapidly Root Cause Post-Silicon Bugs and Validate Fixes
The Questa Post-Silicon Debug app leverages formal analysis, as well as property synthesis, to rapidly give you the observability you need to root cause bugs in logic deep within the SoC, and prove fixes don’t break anything else.
Helping you achieve maximum business impact by addressing your complex technology and enterprise challenges with a unique blend of development experience, design knowledge, and methodology expertise.
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