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Overview

Questa SLEC

Using the “specification” RTL and the “implementation” RTL as input, the Questa SLEC formal app automatically compares the two code blocks using an exhaustive formal analysis. No knowledge of formal or property specification languages is required.

Get in touch with our sales team 1-800-547-3000

image dvt-formal-verification flow diagram - updated 4.22.21
Key Features

Questa Sequential Logic Equivalence Check (SLEC)

Today's designs rely on complex industry standard interfaces that must be verified to ensure IP interoperability and system behavior. Whether a given interface is used without modification, or customized to help differentiate the end-product, integrating even mature IP can produce unexpected issues.

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Automated, exhaustive SLEC

When an Exhaustive Comparison Is Essential

<p>The Questa “SLEC” app uses formal analysis to exhaustively compare the “Specification” and “Implementation” RTL, identifying any differences in the output behavior of the two for all input, and all time. No knowledge of formal or property specification languages is required.</p>

image dvt-formal-verification schematic

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