Questa SLEC
Using the “specification” RTL and the “implementation” RTL as input, the Questa SLEC formal app automatically compares the two code blocks using an exhaustive formal analysis. No knowledge of formal or property specification languages is required.
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Questa Sequential Logic Equivalence Check (SLEC)
Today's designs rely on complex industry standard interfaces that must be verified to ensure IP interoperability and system behavior. Whether a given interface is used without modification, or customized to help differentiate the end-product, integrating even mature IP can produce unexpected issues.
Automated, exhaustive SLEC
When an Exhaustive Comparison Is Essential
The Questa “SLEC” app uses formal analysis to exhaustively compare the “Specification” and “Implementation” RTL, identifying any differences in the output behavior of the two for all input, and all time. No knowledge of formal or property specification languages is required.
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Verification Horizons Blog
Insight and updates on concepts, values, standards, methodologies, and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.
Verification Horizons Issue
The Verification Horizons publication provides concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.
