The Questa Register Check app reads in your RTL and register description file(s), automatically creates the necessary assertions, then formally verifies them. No knowledge of formal or property specification languages is required.
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While testbench simulation-based register verification approaches like UVM_REG can exercise most of the primary use cases, numerous corner-cases are left uncovered, creating the risk of show stopper bugs going undetected.
Verifies expected behavior
The Questa Register Check app automates exhaustive verification of control & status registers. Taking your register spec (in CSV or IP-XACT) and RTL as input, the app automatically derives the properties and runs the formal engines under-the-hood. Any discrepancies in register behavior are graphically shown in detailed waveforms.
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