Comprehensive protocol assertions allow Questa Formal users to exhaustively prove design correctness, while support for Veloce Emulation Systems enables users to easily transition to high-performance simulation acceleration for orders-of-magnitude gains in throughput.
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Today's designs rely on complex industry standard interfaces that must be verified to ensure IP interoperability and system behavior. Whether a given interface is used without modification, or customized to help differentiate the end-product, integrating even mature IP can produce unexpected issues.
Optmized Formal Assertions
Formal proofs with assertion-based IP are partially important when customers modify IP as this enables them to exhaustively prove any customizations or extensions of the standard protocol implementation do not violate the core of the protocol and/or create unexpected corner cases.
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