Questa Formal Assertion

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Overview

Questa Formal Library

Comprehensive protocol assertions allow Questa Formal users to exhaustively prove design correctness, while support for Veloce Emulation Systems enables users to easily transition to high-performance simulation acceleration for orders-of-magnitude gains in throughput.


Get in touch with our sales team 1-800-547-3000

The Questa Formal Assertion Library improves quality and reduces schedule times by building Mentor’s protocol and methodology expertise into packages of reusable assertions that support popular industry-standard interfaces. Because formal verification with Questa PropCheck can start immediately with RTL and assertions only, this frees up engineering resources from having to spend time developing BFMs, verification components, or Verification IPs (VIPs) themselves, enabling them to focus on the unique and high-value aspects of their design.

Questa CoverCheck Resources

IP Caveat Emptor

Shorten time to market by reducing bring-up time

Today's designs rely on complex industry standard interfaces that must be verified to ensure IP interoperability and system behavior. Whether a given interface is used without modification, or customized to help differentiate the end-product, integrating even mature IP can produce unexpected issues.

Optmized Formal Assertions

Formally prove customizations complement the protocol

Formal proofs with assertion-based IP are partially important when customers modify IP as this enables them to exhaustively prove any customizations or extensions of the standard protocol implementation do not violate the core of the protocol and/or create unexpected corner cases.

The Questa Formal Assertion Library improves quality and reduces schedule times by building Mentor’s protocol and methodology expertise into packages of reusable assertions that support popular industry-standard interfaces. Because formal verification with Questa PropCheck can start immediately with RTL and assertions only, this frees up engineering resources from having to spend time developing BFMs, verification components, or Verification IPs (VIPs) themselves, enabling them to focus on the unique and high-value aspects of their design.

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