Exhaustive verification of all static and dynamic connections is completed by the formal engines within a matter of hours vs. the weeks required with test bench simulation-based approaches.
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Previously, a meticulous release engineer could manually inspect the DUT schematic, RTL code, and device specs for any connectivity discrepancies. Today, with modern “correct by construction” code generation tools and linting, the verification of connectivity between IPs in a SoC is a trivial task.
Ease of Use
Automatically derives all the required assertions from your CSV or XML connectivity specifications, and displays them in an easy-to-understand tabular format.
Verifies on-chip bus, inter-block, control signal, clock and reset connections at the sub-system or SoC level. Exhaustively checks all modes of operation.
Completes exhaustive verification of all static and dynamic connections within a matter of hours. "Black boxes" interior areas of the IPs in your RTL to keep focus on the connectivity alone.
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Learn more about formal-based techniques, ranging from formal property checking to formal coverage closure to sequential logic equivalence checking.