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High-Level Verification Solutions

Providing class-leading products and methodology for High-Level design, Siemens delivers solutions at multiple points of the design process. Design Checking, Code and Functional Coverage and Formal verification for C++ and SystemC equivalence checking.

HLS & HLV Upcoming EventsHLS & HLV Resource Library

Catapult High-Level Verification Solutions

Accelerate your High-Level Verification (HLV) flow with known and trusted methods using the Catapult HLV Platform. Reduce your overall SoC verification turnaround time and costs by up to 80% leveraging High-Level Design Checking, Code/Functional Coverage, and static plus formal methods.

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Catapult Coverage

HLS-aware code coverage including support for statement, branch, condition, expression (FEC) and array access coverage plus SystemVerilog-inspired functional coverage with support for covergroups, coverpoints, bins and crosses.

Catapult Formal Verification Tools Flow
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Catapult Formal Verification Tools

Formally find mistakes, ambiguities and problem design issues or user constraint mistakes early in the HLS process. Even with differences in timing, and interfaces, Catapult Formal enables verification and a coverage closure flow.

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SLEC System

Check the correctness of RTL against your High-Level models using SLEC. Enabling proof that specification and implementation are identical despite differences in language, timing, or abstraction.

VIRTUAL HLS SEMINAR

Catapult Customers Discuss their Real-World use of HLS

The past several years have seen an explosion in the adoption of HLS for chip design driven by increasing design and verification complexity as well as time to market pressures. Catapult HLS enables designers to get their chips to market faster by shortening the overall design and verification flow.