Combat escalating validation costs using Tessent Embedded Analytics. Manufacturers of RISC-V-based designs and complex SoCs can use a powerful combination of on-chip instrumentation and software tools that enable functional monitoring, performance analysis and software optimization. The solution is processor-agnostic and provides visibility and analytics in the lab and when systems are deployed in the field.
Identify and resolve errors and bugs significantly faster than when using traditional software-only solutions.
Identify the root cause of under-performance related to CPU, memory and other SoC components.
Monitor and collect data from systems for continuous analysis and optimization.
Listen to Peter Claydon, president of Picocom, along with Gajinder Panesar of Siemens explain how Tessent Embedded Analytics provides non-intrusive monitoring and insights used to optimize Picocom’s 5G small cell network SoCs.
Listen to Richard Bohn, engineering director of advanced IP development at Seagate Technology, describe some of Seagate's challenges and how they use Tessent Embedded Analytics products to improve their debug and optimization.
Traditional SoC development methodologies have failed to keep pace with escalating systemic complexity, creating a productivity gap. Tessent closes that gap, giving engineering teams actionable insights that shorten the total development cycle time, accelerate debug and reduce risk and cost to ensure timely market entry.
Join some of the biggest names in the electronics industry and start using Tessent Embedded Analytics technology. It's supported by an ecosystem of partners, including SoC development tool providers, other silicon IP providers and processor vendors, security experts and silicon design consultancies.
Debugging and optimizing code running on modern SoCs requires a lot of functional analysis due to the dependencies created when combining many processors, hardware blocks, memory, peripherals and software into a system. Toolchains must be optimized so that embedded application code can take maximum advantage of the target architecture. Delivering on the promised compute performance requires a cycle of hardware, software optimization and testing that starts in emulation and continues through the test chip and into the field. System architects must be able to run functional analysis on the chip to answer questions, such as: how effectively data is shared across buses, is the NoC balanced, how efficient is the branch predictor, is the code partitioning optimal, are there any potential SRAM bottlenecks? As well as debugging their code, software engineers need to understand functional behavior including how events across all SoC components correlate if an application crashes or resets, whether any threads overrun a timing window and which block of memory to use for data.
Use Tessent Embedded Analytics IP modules to capture the data required to analyze many-core systems. Combined with intelligent software, the Embedded Analytics platform of hardware IP provides a unique functional analysis solution that goes far beyond monitoring of on-chip process parameters to provide full system-level visibility. This enables optimization through the lifecycle of the device.
Tessent Embedded Analytic systems use a highly optimized message format to transport different types of data between the analytic modules and on-chip or host software applications. Blocks of instruction/data processor trace can be encapsulated in an Embedded Analytic message with a timestamp and output over fast PCIe or Serdes ports for analysis in host applications. Alternatively, configuration data can be sent from an embedded or host application to configure features of the IP modules such as filters or comparators. Embedded Analytic messages are compressed to ensure that only the optimum amount of data is transferred between the hardware and software.
The underlying message fabric enables real-time communication between all the Embedded Analytic modules in a system. For example, when a Bus Monitor identifies a transaction of interest, it can send an event to a processor analytic module (JPAM/BPAM) to stop a processor, instruct an Enhanced Trace Encoder to capture processor instruction trace immediately prior to the event and trigger the DMA to dump the value in a memory block at a particular address. The global reset event is often used to capture enough data to reconstruct the general state of the system prior to the reset call.
Hardware bus deadlocks often occur when a processor stalls, waiting for a response from another on-chip subsystem via the system bus. The protocol-aware Embedded Analytics Bus Monitor can be set up to trigger when the time taken for a bus transaction exceeds a programmable limit or a transaction does not have the correct privilege level. When triggered by a deadlocked transaction, the Bus Monitor identifies the complete transaction ID and address, guiding the engineer to the problem transaction.
Software deadlocks are increasingly common in SoCs with multiple CPUs, particularly where different software processes use a locking mechanism to govern shared access to common on-chip resources. The Embedded Analytics Status Monitor can be configured to detect the fault condition, send a real-time event to other Embedded Analytic modules (processor analytic modules) to halt the processors, and then initiate data capture to identify and isolate the problem.
The Efficient RISC-V Trace specification includes the following mandatory features:
Optional features (ISA extensions) include:
The Tessent Enhanced Trace Encoder from Siemens EDA includes all the mandatory and optional features. It also includes: