HyperLynx Hybrid Solver

The HyperLynx Hybrid Solver is a decompositional solver designed to create electromagnetic models for layered electronic structures like PCBs and flexible cables. It is tightly integrated with HyperLynx Signal and Power Integrity to provide accurate, automated system analysis workflows.

Hybrid solver applications

The HyperLynx Hybrid solver decomposes a design into traces, planes & vias by creating a model for each section and then solving for overall behavior using a variety of different solver methods. It assumes the structure is planar (or in the case of cables, a cross-section) such that these analytical techniques are valid. Hybrid solvers are less compute and memory intensive than full-wave solving and can model larger structures as a result. Where the "cut and stitch" method is used to model signal paths with a full wave solver, a hybrid solver models the entire signal path and performs the decomposition in the solver.

The HyperLynx Hybrid solver is ideally suited for performing power-aware analysis of entire DDR interfaces, where capturing the effects of return path current sharing and Simultaneous Switching Noise (SSN) are important. It is also ideally suited for full-board AC power integrity, modeling decoupling capacitors and power delivery to IC pins. The Hybrid solver is especially well suited to power integrity because it models partial power planes and associated fringing effects.

Return path analysis

Power-aware signal integrity

Traditional signal integrity assumes that signals have ideal return paths; always existing over a reference plane, with no reference discontinuity when switching signal plane layers. It is also traditionally assumed ideal power is delivered to the device's output buffers.

In the real world, return currents flowing on one reference plane must find a continuous electrical path to another, which usually involves nearby stitching vias. Any diversion of the return current creates additional inductance that impacts signal behavior and can result in coupling between signals through a phenomenon known as return current sharing. Similarly, the power rail at an output buffer is not ideal, and the driver voltage can droop if many outputs switch simultaneously in the same direction. The amount of voltage droop is determined by the output edge rate, the driver strength, a switching effect known as crowbar current and the amount of high-frequency capacitive decoupling that services that area of the die. Output power rail droop reduces the power available to the output driver, softening and slowing the output edge rate. This phenomenon is known as Simultaneous Switching Noise, or SSN. SSN reduces signal operating margins and, in severe cases, can close the available eye at the receiver input.

Using an ideal signal return path allows for fast modeling but neglects the effects of trace over split, return path sharing due to inadequate stitching vias, coupling between signal vias and signal via crosstalk through the power cavity. Including these effects provides a more realistic estimate of operating margin at the cost of more modeling and simulation compute time. Including these effects will only ever reduce design margin, not increase it. It makes sense to run analysis with idealized return paths first - because if the design doesn't pass in the ideal case, it won't pass in a more realistic one.

Using ideal IC power neglects the effects of SSN, while including an accurate model of the board's power delivery characteristics to the IC pins allows these effects to be quantified. This analysis requires a power-aware IBIS model for the IC and slows the simulation process. For the same reasons as before, these effects should only be considered once a design passes analysis with ideal power.

Correctly modeling and simulating the effects of non-ideal return paths and SSN requires an accurate interconnect model that includes the combined behaviors of signal traces and the board's Power-Delivery Network (PDN). The HyperLynx Hybrid solver can create these combined interconnect models directly from BoardSim - the user specifies the signals and frequencies of interest, and the Hybrid solver creates a S-parameter model ready for direct inclusion into BoardSim simulations.

PCB-level power integrity

Modern printed circuit boards have multiple power supplies, some of which are only partial planes on certain layers of the board. Modeling power delivery accurately requires correctly modeling these partial planes together with decoupling capacitors and associated component parasitics, and the loop inductances of each capacitor's fanout structure. The location of power and ground planes within the stackup, as well as capacitor location and fanout have a big effect on the impedance characteristic of the Power Delivery Network (PDN) as seen by the different ICs.

Components consume power at a wide range of frequencies, from DC up to their internal switching speeds (usually in the GHz). Simply providing lots of power at DC isn't enough, because when a high speed circuit switches, it creates an instantaneous demand for power to support the switching event. Because EM waves travel at finite speed, there isn't time for the demand for additional power to flow to the VRM and back - there has to be a local reservoir of charge (a capacitor) that can be tapped. That's the role decoupling capacitors play in Power Delivery Networks.

In practice, the PDN is a distributed hierarchy of capacitors that begins with the voltage regulator (VRM) and ends with capacitors on the IC die itself. In between, there are a variety of capacitors on the board that range from bulk to small devices like 0204s, optional capacitors on the IC package and capacitive structures that are part of the IC layout. Each group of capacitors services demands for power at successively higher frequencies, with the highest frequency capacitors being on the die itself.

Inductance is the primary limiting factor for decoupling capacitors, because it limits the frequencies that a given capacitor can service. Thus, capacitor value, placement and fanout are critical features for high-frequency PCB and package capacitors. The inductance associated with the IC package's power and ground pins effectively filters the power delivered to the IC; beyond a certain point, it doesn't matter whether the PCB can supply high frequency power or not, because it wouldn't make it through the PC package to the die. The package and IC package must carry the load forward from that point.

As a result, AC power integrity at the board level typically concerns itself with frequencies that start at the VRM's upper limit (typically 5-25 kHZ) and end at the power cutoff frequency for the IC package (typically 25-100 MHz). The cutoff frequency for the IC package typically decreases as the packages get bigger, because the package inductance increases and the package therefore has to carry more of the high-frequency load.

When analyzing a PCB PDN, it's critically important to model the decoupling capacitors and their inherent parasitic inductances and resistances, the details of capacitor fanout and the capacitor locations and values. The impedance of the PDN is probed at different IC pins to determine the PDN profile seen at each IC.

When a PCB has simple power plane layers where an entire plane is ground or a single power supply, fast AC analysis methods can be applied - but few modern PCBs are made that way. When the power and ground planes become irregular, more detailed modeling is needed to capture their behavior. The HyperLynx Hybrid solver can accurately capture the behavior of arbitrarily shaped power and ground planes, including the use of long, wide traces to deliver power to individual components. The Hybrid solver is seamlessly integrated into the Advanced Decoupling workflow, so once the user identifies the voltage supply to be analyzed and sets it up, the Hybrid solver does the rest.

HyperLynx integration and ease of use

The HyperLynx hybrid solver serves as a tightly integrated part of signal and power integrity workflows. Within these workflows, automated analysis wizards guide users through the setup and analysis processes step-by-step. Users step through the wizards answering the questions on each page, and HyperLynx does the rest!

Within the HL-SI DDR SI power-aware workflow, the hybrid solver is used to create a system model that includes the high-speed DDR signals, along with the PDN and their interactions. This model is used to examine the effects of both non-ideal return paths and simultaneous switching noise.

Within the HL-PI advanced decoupling workflow, the hybrid solver is used to create a model of the PCB that includes the VRM, the board-level PDN, decoupling capacitors and the IC pins where the PDN impedance is to be analyzed.

In each case, board level characteristics are automatically extracted and used to create ready-to-run projects for the solver, which are solved and post-processed to produce efficient, accurate, passive, causal S-parameter models that are then incorporated into system-level simulations. The S-parameter models output by the hybrid solver document the analysis and connection details for each port to ensure proper connectivity when the full system netlist is constructed.

Scripting & automation

Signal and Power Integrity Analysis are complex, multi-step processes, where changing a single option can significantly affect the end result. Because these simulations are often lengthy, compute and memory-intensive, ensuring that simulations are set up properly and performed consistently is critical. Without the ability to ensure that simulations are performed consistently and accurately, much time is lost adjusting and resimulating.

HyperLynx Advanced Solvers can be run both interactively and through Python-based automation. This allows designs to be initially set up, analyzed and debugged using interactive analysis to determine optimal simulation settings. Then, as the design is iterated, those settings can be reused through automation to ensure analysis is always run the same way, reports on the same metrics and produces the same output models. An interactive, command-line scripting environment is available directly with the solvers so that users can develop and test their automation scripts.

HyperLynx Advanced Solver automation is part of a broader scripting framework for the full HyperLynx family, that allows automated multi-tool analysis flows to be created. This object-oriented scripting framework includes pre-defined flows for power integrity, signal integrity and serial link compliance analysis that allow users to run complex analyses with just a few lines of custom code.