Complete signal integrity solution
The HyperLynx family includes all the tools you need for complex signal integrity analysis – expert-based design rule checking, 2D and 3D electromagnetic modeling, standards-based, protocol-aware simulation & comprehensive HTML-based rules reporting. HyperLynx supports both pre-layout design space exploration and system-level post-route verification using the same analysis flows, making it easy to compare your pre-layout performance predictions with actual results based on the completed layout.
Ease of use
Products in the HyperLynx family are pre-integrated with proven workflows, so there’s no need to worry about converting or formatting data when moving between tools. Not only are base workflows already defined and proven; they’re automated using analysis wizards that guide you through the analysis process step by step –you just need to fill in the blanks and hit “Run”. With HyperLynx’s world-renowned ease of use, performing complex signal integrity simulations has never been easier. If you’re new to HyperLynx, HyperLynx workshops provide working examples with databases, simulation models and step by step instructions that will get you up and running fast. HyperLynx workshops are available 24/7, so you can learn new skills on-demand.
DDR interface analysis
HyperLynx provides complete interface-level analysis for DDR3/LPDDR3, DDR4/LPDDR4 and DDR5/LPDDR5 memories, verifying all signals for signal quality and inter-signal timing requirements. HyperLynx understands the requirements associated with each version of the JEDEC standard and changes the analytical flow and metric targets accordingly. HyperLynx can also model controller-specific signal integrity and timing behaviors, factoring them into the analysis. HyperLynx produces a complete report for all interface signals, showing which signals passed, which signals failed which tests, and by how much.
Serial link analysis
HyperLynx uses a Progressive Verification approach for dealing with serial links, first analyzing the physical interconnect for compliance with the associated protocol standard, then adding in vendor-specific IBIS-AMI models and device settings to perform device-specific analysis. Automated compliance analysis supports 237 protocols and variants, including Ethernet, fiber channel, HDMI, JESD, MIPI D, OIF-CEI, PCIE, USB. Most importantly, Compliance Analysis works even when vendor simulation models for the components aren’t available. Post-layout channel model extraction is entirely automated, including 3D full-wave solvers to model component breakouts and via transitions, so all the serial channels in the design can be analyzed.
General-purpose signal integrity
Not all the signals in each design are associated with a hardware standard. For those signals, HyperLynx supports classic signal integrity analysis to predict signal quality and eye closure due to impedance mismatches and resulting inter-symbol interference (ISI), considering the effects of topology, drive impedance and slew rate, termination, signal spacing and crosstalk. Individual signals can simulated and investigated interactively, or entire groups of signals can be analyzed and reported using batch analysis.
Dive deeper into this topic
What is signal integrity analysis and how does someone know they need signal integrity analysis? Learn more by reading our blog on signal integrity analysis or by listening to this podcast on the power of simulation and analysis in PCB design.