Overview
HyperLynx DDRx Design and Verification
HyperLynx streamlines DDR3/4/5 interface analysis by automating compliance checks for signal integrity and timing, providing a consistent workflow from pre-layout to post-layout simulation stages.
Powerful, Automated DDRx Simulation
HyperLynx provides a complete flow for DDRx EM modeling & simulation that understands protocol and component-specific requirements. Actual operating design margins are clearly reported in mV and pS, enabling designers to quickly determine if their design will pass or fail and by how much.
Automated Post-layout Verification
Post-layout analysis automatically extracts detailed interconnect models from layout based on the user’s selections of nets to simulate and crosstalk settings. The resulting models are automatically simulated to determine the design’s compliance with protocol and component-specific signal integrity and timing requirements. Automated post-layout verification supports both single and multi-board designs.
Pre-layout Design Exploration
HyperLynx lets designers evaluate alternatives to optimize for cost and performance while ensuring the design meets stringent signal integrity and timing requirements. Designers can assess the relative impacts of trace length, impedance, routing layer, spacing, and relative length, in addition to via design, drive strength, receiver termination and more to determine the right combination for their design.
Unified, Automated Analysis Workflow
HyperLynx provides a single, consistent workflow for pre- and post-layout simulation. Performing the same analysis, the same way, with the same output reporting allows designers to compare post-layout verification results to their pre-layout counterparts to determine if layout rules were followed correctly. Where results differ, HyperLynx “what if” analysis helps designers find and resolve issues quickly.
Comprehensive Design Margin Reporting
HyperLynx provides DDRx signal integrity and timing results in a comprehensive report that can be shared with others. All signal relationships are covered, including data read/write, address and clock/DQS. Design margins are reported in mV and pS, linked to waveforms that show how critical measurements were made. The report includes links to eye diagram displays that can be examined interactively.
Advanced Analysis Support
HyperLynx accurately analyzes high-speed, densely routed DDR designs. Post-layout crosstalk automatically includes aggressors based on user-defined coupling thresholds. Power-Aware analysis integrates 3D EM modeling to include PDN effects like SSN and non-ideal signal return paths. DDR5 analysis supports IBIS-AMI models and accurate models the impact of rise/fall asymmetry on design margins.
