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hyperlynx signal integrity eye diagram

HyperLynx Signal Integrity

HyperLynx is a complete Signal Integrity (SI) solution for high-speed digital pre-layout exploration and post-layout verification. Double data rate (DDR) interfaces, high-speed serial channels and general-purpose signals can be analyzed for signal quality requirements and operating margins.

The importance of signal integrity

Signal integrity is the analog analysis of the switching behavior of high-speed digital signals. What determines whether the signal is “high-speed” and should be considered for signal integrity purposes isn't the data rate; it's the output driver's edge rate. Once a signal's electrical length (delay) exceeds 1/4 of the driver's rise time, the signal becomes prone to problems with reflections and ringing if impedances aren't carefully managed. This is the threshold where signal integrity becomes important. Signals with low data rates can still have problems with ringing and reflections because signal integrity is about the edge rate, not the data rate.

Against that backdrop, signal data rates continue to increase dramatically, with edge rates decreasing to keep up. Meanwhile, printed circuit boards (PCBs) aren't getting smaller, so signal integrity issues are becoming pervasive. 250ps is a typical output edge rate for modern devices; at this point, traces longer than 0.375 inches should be considered for signal integrity purposes. The need to consider signal integrity is pervasive in modern design.

To keep the designer’s tasks manageable, many component interfaces are based on standards that define how signals are to be connected and what their electrical characteristics should be. DDR memory and serial link protocols like Ethernet are good examples. If the signal traces conform to these specifications and the components meet or exceed the specifications, the interface should work. That said, many interface standards specify electrical characteristics like impedance, loss, crosstalk, skew and eye openings, that require detailed modeling and simulation to predict. HyperLynx SI is an ideal solution to these issues.

HyperLynx signal integrity applications

HyperLynx provides a comprehensive set of Signal Integrity tools that simplify and automate signal integrity analysis. This makes sophisticated analysis more accessible to system designers, which in turn helps streamline your design process and reduce the workload of dedicated SI experts.

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DDR interface analysis

HyperLynx provides complete, interface-level analysis for DDR3-5 and LPDDR3-5 memories, simulating and analyzing signal quality and inter-group timing requirements. Understanding each version of the Solid State Technology Association (JEDEC) standard changing the analytical flow and analysis metrics accordingly. HyperLynx models controller-specific signal integrity and timing behaviors as part of the analysis.

DDRx Design simulation showing a DDR4 PCB simulation.

Progressive verification

HyperLynx’s unique progressive verification methodology lets you find problems faster with less effort, allowing you to make the best use of your valuable SI experts. Learn how compliance analysis allows you to perform analysis without vendor simulation models and explore our automated post-layout channel model extraction, which ensures all of the serial channels in the design can be analyzed.

HyperLynx Progressive Verification signal integrity analysis summary

Integrated stackup editor

hyperlynx general PCB signal integrity stackup editor for signal integrity analysis

Correctly modeling a PCB stackup is the foundation of accurate simulation results. Not all stackups are created equal; the exact materials, properties and dimensions used to fabricate the board must be specified for simulation results to match the actual PCB. This information is usually not correct in the PCB database received from layout designers, and it often changes when a particular fabricator is selected to build the board.

The HyperLynx stackup editor lets designers manage stackup data to ensure that it reflects the board as it will be built. They can view and edit the properties for each layer independently, specify trace surface roughness and changes to trace geometries as the result of manufacturing. The HyperLynx stackup editor can import stackup data directly from Z-Zero Z-Planner, which allows designers to select materials from a large material database and model the effects of different board assembly schemes.

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