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Serial Channel Verification

HyperLynx Serial Channel Design & Verification

HyperLynx performs both standards-based interconnect Compliance Analysis and vendor model-based IBIS-AMI simulation for high-speed serial links. System-level, automated post-route analysis includes full topology extraction using integrated, 3D EM modeling with scalable performance.

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The broadest standards support

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HyperLynx supports over 250 different protocols and variants from the Ethernet, Fiber Channel, HDMI, JESD, MIPI D-PHY, OIF-CEI, PCI-e and USB families.

Serial links must conform to requirements in associated standards specification documents. These specifications lay out requirements for the transmitter (Tx) device and IC package, pin-to-pin system level interconnect and the receiver (Rx) device and IC package. These documents are long (often hundreds of pages) and detailed. Understanding just one standard completely is a huge task - but there are dozens of them, with hundreds of variants.

Siemens experts study each of these standards to create simulation setups that configure HyperLynx to perform the correct analysis flow and report the metrics associated with each standard protocol.

Each analysis type is specified via a built-in configuration file that automatically sets up channel speed, modulation, stimulus encoding, analysis flow and metric reporting for both Compliance Analysis and IBIS-AMI simulation. These configuration files can be copied and modified using a built-in editor, and new configurations can be added when available. HyperLynx also includes a set of "generic" setups that are useful for quick what-if analysis and prototyping support for new protocols.

Integrated 3D EM modeling

Full-wave 3D electromagnetic modeling of BGA and connector breakouts, via transitions and blocking capacitors is essential for accurate analysis of serial links at speeds beyond 5 GT/s. Without accurate 3D EM models for these areas, system-level margins cannot be determined accurately.

The full end to end channel model is constructed from a variety of different elements that typically include vendor-supplied S-parameter files (IC packages and connectors), trace models including surface roughness effects, and S-parameter files from 3D EM solvers to represent PCB breakout, via and blocking capacitor structures. The process of dividing the routing into sections and then building up the full trace model from the associated models is known as cut and stitch modeling. It's critical that models for the individual sections are specified in a way that allows them to be cascaded together without introducing error. HyperLynx automates this process to produce complete topology models for serial links. The channel model is created based on knowledge of the protocol being analyzed so it conforms to the protocol requirements for model resolution and bandwidth.

When extracting a topology model for a serial link, HyperLynx first uses an embedded DRC engine to identify areas that require 3D EM modeling. An area containing the signal and its return path are identified, then a corresponding 3D EM solver project is created. This analysis is performed across all the channels being analyzed, and the 3D areas are compared so that any identical areas are not solved twice. The resulting areas are then solved automatically and complete channel end to end models are created for simulation and results processing. HyperLynx automates this entire process - the designer specifies the signals of interest and criteria for identifying an aggressor signal - and HyperLynx does the rest. This process provides full channel modeling accuracy comparable to modeling the entire channel in a 3D solver, at a fraction of the compute and memory cost.

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For large designs with hundreds of channels and thousands of areas, HyperLynx scales 3D solver performance by running solvers in parallel over a LAN, either by leveraging load management facilities already installed at the customer's site, or using its own internal Job Distribution facility.

Superior standards compliance analysis

Protocol Compliance Analysis examines the pin-to-pin system level interconnect in a design to ensure it meets the requirements of the applicable protocol standard. It leverages the system interconnect requirements published as part of the standard itself. Compliance Analysis is especially useful because most system designers use off-the-shelf ICs; they don't create either the ICs they use or the associated IC packages. Compliance Analysis focuses on what system designers actually create: system boards. Until now, the only way most system designers had to validate their work was to run a link simulation using vendor-supplied component (IBIS-AMI) models. This adds a layer of complication because IBIS-AMI models are often hard to obtain and validate, and the process to set up simulations and interpret results often varies from model to model.

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Serial link standards specify detailed requirements for system interconnect that can be verified analytically. Since system designers are typically responsible for the design of PCB interconnect that uses off-the-shelf components, it makes sense to analyze and optimize the design of the system interconnect by itself. That's exactly what HyperLynx Compliance Analysis does. Compliance Analysis works when vendor (IBIS-AMI) models are not available, so it can always be run on a design. The HyperLynx Compliance Analysis flow is the same no matter which vendor's components are used, which means it can be learned once and used across different designs and component vendors - instead of changing each time. The HyperLynx flow is even constant across multiple protocols, as opposed to other standards-based techniques that vary the tools used and analytical methodology from protocol to protocol.

HyperLynx Compliance Analysis produces a comprehensive HTML report that shows how channel characteristics compare to time and frequency requirements. Channel operating margins using a "spec" Tx and Rx are shown, along with automatically determined optimal equalizer settings used to perform the analysis. The report contains a wealth of detailed data that is useful for determining how the channel design could be improved.

Compliance Analysis is faster and easier to run than simulation with vendor IBIS-AMI models. If Compliance Analysis shows that a design will work with spec-based Tx and Rx devices, AND the actual component vendor's devices meet or exceed the standard - then the complete system should be expected to work. IBIS-AMI analysis is still recommended for design signoff, but Compliance Analysis is an ideal way to screen and debug designs before investing the time and effort investment required for full IBIS-AMI simulation.

IBIS-AMI simulation

Simulation with vendor-supplied (IBIS-AMI) models is the most accurate form of serial link analysis, because it models the actual devices and equalization capabilities that will be used for the Tx and Rx in a serial link. Where the actual ICs exceed the requirements of the standard, those behaviors will be reflected in an increased operating margin for the link. Because IBIS-AMI models reflect the actual equalization capabilities and settings of the physical devices, simulation can be used to determine the equalization settings that should be implemented at the system level.

This increased accuracy, however, comes at a price - the effort required to obtain and validate IBIS-AMI models for use, along with the additional effort needed to configure simulations and interpret simulation results. IBIS-AMI models come in 3 main varieties, often called Statistical (Init-only), Time-Domain (Getwave-only) and Dual (both Init and Getwave) models. This means that analysis flows will vary between different combinations of models, because analysis flows are driven by the model types being used in the simulation. Using IBIS-AMI models effectively requires understanding the different model types and their proper application; typically a task for dedicated simulation specialists. For this reason, deferring expertise-intensive IBIS-AMI simulation is recommended, using Compliance Analysis first to identify and resolve as many issues as possible. One additional benefit is that the channel models constructed for Compliance Analysis can be directly reused for IBIS-AMI simulation, so all the detailed channel modeling work is already done!

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Overview

SERDES channel equalization for serial interfaces

The newer industry-standard SerDes protocols such as PCIe Gen6, USB4, and the 100G per-lane Ethernet and OIF/CEI standards offer several unique challenges for PCB designers. While speeds are approximately doubling for each generation, the dielectric material used remains the same across generations. To compensate for the increased loss at higher data rates, complex equalization techniques are employed.

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