Tessent Advanced DFT
Tessent Streaming Scan Network
Tessent Streaming Scan Network packetizes test data to dramatically reduce DFT implementation effort and reduce manufacturing test cost. By decoupling core-level and chip-level DFT requirements, each core can be designed with the most optimal compression configuration for that core.
Why Tessent Streaming Scan Network?
Tessent Streaming Scan Network delivers the promise of true hierarchical plug-n-play DFT. By decoupling core-level DFT configuration from chip level DFT resources, the DFT planning and implementation effort is dramatically reduced while simultaneously reducing manufacturing test cost.
Accelerate time-to-market
Realize a 10x productivity gain using simplified chip-level planning. By decoupling core- and chip-level DFT, core-level compression can be optimized without considering other cores or chip-level resources.
Lower test costs
By combining automatic bandwidth tuning and local generation of DFT signals, whitespace in the pattern is virtually eliminated.
Reduce power profile by up to 90%
SSN provides a smoother power profile using staggered shift/capture clocks and better concurrency. Concurrent cores to be tested can be selected programmatically rather than during design without impacting chip-level routing.
How SSN Accelerates Time to Market
A traditional hierarchical scan test approach has specific challenges, which can be drastically improved using a packetized test delivery mechanism. Tessent Streaming Scan Network (SSN) reduces the DFT planning and implementation effort up to 5x using packetized test delivery. See what Pete Orlando has to say about the latest news on Tessent SSN.
Using Veloce DFT app to rapidly accelerate quality
Robert Serphillips, DFT/Fault Product Manager, discusses how using the Veloce DFT app can rapidly accelerate quality and lower test costs.
With Tessent Streaming Scan Network technology, we are able to offer our customers a scalable test access solution ideal for today’s and tomorrow’s advanced IC designs. SSN significantly reduces the effort needed to make complex designs highly testable.