Tessent Connect reduces DFT implementation effort with an optimal automation of the Tessent Shell flow for hierarchical DFT. This addresses the challenges of implementing hierarchical DFT by using intent-driven automation, universal test infrastructure, and future-proof customization.
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Tessent Connect helps IC design teams achieve manufacturing test quality goals faster and with fewer resources compared to traditional DFT methods. This production-proven automation enables a simple, consolidated hand-off between teams, resulting in a sustainable and predictable flow.
Faster DFT implementation
<p>With Tessent Connect, you define your intent rather than step-by-step instructions. This is made possible with specification-based IP insertion, a single, unified database, and Tessent Core Description based data transfer. DFT IP and Signals are automatically configured for all test modes. </p>
<p>By leveraging IEEE 1687 (IJTAG) infrastructure, insertion, ICL extraction, and PDL retargeting is supported for Tessent as well as third-party IP. Multiple chip-level interfaces are supported for manufacturing and in-system test, including IEEE 1149.1, IEEE 1500, and I2C. </p>
Flexible use models
<p>With integrated introspection and design editing customizations across the flow, your flow can be customized in a sustainable way. Custom DRCs, user-defined commands, and custom pre- or post-insertion scripts can be utilized across the flow. </p>
"eSilicon uses Tessent Connect to help us meet our aggressive production schedules and deliver industry-leading ICs like those based on eSilicon’s neuASIC 7nm platform for machine learning."
Joseph Reynick, Director of DFT services , eSilicon
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